Bump Wafer Level Packaging A New Packaging Platform (not only) for Memory Products

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 5288, Issue , 2003, Pages 681-686

  Hedler, Harry ^a   Meyer, Thorsten ^a   Leiberg, Wolfgang ^a   Irsigler, Roland ^a  

^a INFINEON TECHNOLOGIES AG   (Germany)

Author keywords

Flexible interconnect; Printing; Wafer level packaging; Wafer level test; Wafer scale assembly

Indexed keywords

COSTS; ELECTRONICS INDUSTRY; LARGE SCALE SYSTEMS; MATERIALS TESTING; PRINTED CIRCUIT BOARDS; PRINTING; PRODUCTION ENGINEERING; RELIABILITY; TECHNOLOGY;

FLEXIBLE INTERCONNECT; WAFER LEVEL PACKAGING; WAFER LEVEL TESTS; WAFER SCALE ASSEMBLY;

ELECTRONICS PACKAGING;

EID: 2342453304     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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