Serrated chip morphology and comparison with finite element simulations

American Society of Mechanical Engineers, Manufacturing Engineering Division, MED

Volumn 15, Issue , 2004, Pages 815-824

  Deshayes, L ^a   Mabrouki, T ^b   Ivester, R ^a   Rigal, J F ^b  

^a NIST Manufacturing Engineering Laboratory   (United States)

^b UNIVERSITÉ DE LYON   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP FORMATION; CHIP MORPHOLOGY; FINITE ELEMENT SIMULATION; HARDNESS MEASUREMENTS;

COMPUTER SIMULATION; COMPUTER SOFTWARE; FINITE ELEMENT METHOD; HARDNESS; MICROPROCESSOR CHIPS; MORPHOLOGY; STEEL; STRAIN RATE;

MACHINING;

EID: 23244444396     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1115/IMECE2004-60717     Document Type: Conference Paper

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