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Volumn 2391, Issue , 2002, Pages 370-389

Timing analysis of assembler code control-flow paths

Author keywords

[No Author keywords available]

Indexed keywords

CODES (SYMBOLS); HIGH LEVEL LANGUAGES; ITERATIVE METHODS; SAFETY ENGINEERING; SEMANTICS; TIMING CIRCUITS;

EID: 23044532638     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-45614-7_21     Document Type: Conference Paper
Times cited : (5)

References (20)
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    • R.-J. R. Back and J. von Wright. Refinement calculus, part I: Sequential nondeterministic programs. In J. W. de Bakker, W.-P. de Roever, and G. Rozenberg, editors, Stepwise Refinement of Distributed Systems: Models, Formalisms, Correctness (REX Workshop 1989), volume 430 of Lecture Notes in Computer Science, pages 42-66. Springer-Verlag, 1989.
    • (1989) Stepwise Refinement of Distributed Systems: Models, Formalisms, Correctness (REX Workshop 1989) , pp. 42-66
    • Back, R.-J.R.1    Von Wright, J.2
  • 3
    • 0008629626 scopus 로고
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    • (1989) High-Integrity Software , pp. 176-197
    • Carré, B.1
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    • 0035242050 scopus 로고    scopus 로고
    • A sequential real-time refinement calculus
    • I. J. Hayes and M. Utting. A sequential real-time refinement calculus. Acta Informatica, 37(6):385-448, 2001.
    • (2001) Acta Informatica , vol.37 , Issue.6 , pp. 385-448
    • Hayes, I.J.1    Utting, M.2
  • 12
    • 0029517739 scopus 로고
    • Integratingthe timinganalysis of pipeliningand instruction caching
    • IEEE Computer Society Press, December
    • C. A. Healy, D. B. Whalley, and M. G. Harmon. Integratingthe timinganalysis of pipeliningand instruction caching. In Proc. 16th IEEE Real-Time Systems Symposium, pages 288-297. IEEE Computer Society Press, December 1995.
    • (1995) Proc. 16Th IEEE Real-Time Systems Symposium , pp. 288-297
    • Healy, C.A.1    Whalley, D.B.2    Harmon, M.G.3
  • 13
    • 84937411068 scopus 로고
    • A layered real-time specification of a RISC processor
    • H. Langmaack, W.-P. de Roever, and J. Vytopil, editors, volume 863 of Lecture Notes in Computer Science, Springer-Verlag
    • P. Kearney and M. Utting. A layered real-time specification of a RISC processor. In H. Langmaack, W.-P. de Roever, and J. Vytopil, editors, Formal Techniques in Real Time and Fault Tolerant Systems, volume 863 of Lecture Notes in Computer Science, pages 455-475. Springer-Verlag, 1994.
    • (1994) Formal Techniques in Real Time and Fault Tolerant Systems , pp. 455-475
    • Kearney, P.1    Utting, M.2
  • 14
    • 0033355604 scopus 로고    scopus 로고
    • An integrated path and timing analysis method based on cycle-level symbolic execution
    • November
    • T. Lundqvist and P. Stenström. An integrated path and timing analysis method based on cycle-level symbolic execution. Real-Time Systems, 17(2/3):183-207, November 1999.
    • (1999) Real-Time Systems , vol.17 , Issue.2-3 , pp. 183-207
    • Lundqvist, T.1    Stenström, P.2
  • 18
    • 84937400446 scopus 로고    scopus 로고
    • An Algebraic Approach to Compiler Design, volume 4 of AMAST Series in Computing
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    • Sampaio, A.1
  • 19
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    • Technical Report 93-25, Software Verification Research Centre, The University of Queensland, February
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    • (1994) Instruction Level Specification of a MIPS R3000 CPU
    • Uttingand, M.1    Kearney, P.2
  • 20
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    • T. Williams. Performance pushes RISC chips into real-time roles. Computer Design, pages 79-86, September 1991.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.