FPGA-based configurable systolic architecture for window-based image processing

Eurasip Journal on Applied Signal Processing

Volumn 2005, Issue 7, 2005, Pages 1024-1034

  Torres Huitzil, César ^a   Arias Estrada, Miguel ^a  

^a INSTITUTO NACIONAL DE ASTROFÍSICA   (Mexico)

Author keywords

Configurable system; FPGA; Real time; Systolic array; Window based image processing

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; COMPUTER VISION; DATA REDUCTION; FIELD PROGRAMMABLE GATE ARRAYS; IMAGE PROCESSING; REAL TIME SYSTEMS; REDUNDANCY; THROUGHPUT; VIRTUAL REALITY;

CONFIGURABLE SYSTEMS; HARDWARE UTILIZATION; REAL TIME; WINDOW-BASED IMAGE PROCESSING;

SYSTOLIC ARRAYS;

EID: 22944482531     PISSN: 11108657     EISSN: None     Source Type: Journal    
DOI: 10.1155/ASP.2005.1024     Document Type: Article

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