Leakage power analysis and reduction: Models, estimation and tools

IEE Proceedings: Computers and Digital Techniques

Volumn 152, Issue 3, 2005, Pages 353-368

  Agarwal, A ^a   Mukhopadhyay, S ^a   Kim, C H ^a   Raychowdhury, A ^a   Roy, K ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC FIELD EFFECTS; ELECTRIC RESISTANCE; ELECTRON TUNNELING; GATES (TRANSISTOR); LEAKAGE CURRENTS; LOGIC CIRCUITS; MOSFET DEVICES; THRESHOLD VOLTAGE;

CHANNEL LENGTH; DRAIN-INDUCED BARRIER LOWERING (DIBL); SUBTHRESHOLD LEAKAGE; SUPPLY VOLTAGE;

POWER ELECTRONICS;

EID: 22944460764     PISSN: 13502387     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1049/ip-cdt:20045084     Document Type: Conference Paper

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