A pipeline architecture for computing the Euler number of a binary image

Journal of Systems Architecture

Volumn 51, Issue 8, 2005, Pages 470-487

  Bishnu, Arijit ^a   Bhattacharya, Bhargab B ^b   Kundu, Malay K ^b   Murthy, C A ^b   Acharya, Tinku ^c  

^a JAPAN ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY   (Japan)

^b INDIAN STATISTICAL INSTITUTE   (India)

^c Avisere Inc   (United States)

Author keywords

Euler number; Image processing; Pipeline architecture; VLSI implementation

Indexed keywords

ALGORITHMS; COMPUTATION THEORY; COMPUTER HARDWARE; IMAGE ANALYSIS; IMAGE PROCESSING; MATRIX ALGEBRA; TOPOLOGY; VLSI CIRCUITS;

EULER NUMBERS; PIPELINE ARCHITECTURE; PIXEL; VLSI IMPLEMENTATION;

COMPUTER ARCHITECTURE;

EID: 22144499596     PISSN: 13837621     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sysarc.2004.12.001     Document Type: Article

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