Error rate test of large-scale SFQ digital circuit systems

IEEE Transactions on Applied Superconductivity

Volumn 15, Issue 2 PART I, 2005, Pages 427-430

  Fujiwara, Kan ^a   Nakajima, Naoki ^a   Nishigai, Takanobu ^a   Ito, Maki ^a   Yoshikawa, Nobuyuki ^a   Fujimaki, Akira ^b   Terai, Hirotaka ^c   Yorozu, Sinichi ^d  

^a YOKOHAMA NATIONAL UNIVERSITY   (Japan)

^b NAGOYA UNIVERSITY   (Japan)

^c NATIONAL INSTITUTE OF INFORMATION AND COMMUNICATIONS TECHNOLOGY   (Japan)

^d SUPERCONDUCTIVITY RESEARCH LABORATORY   (Japan)

Author keywords

Bit error rate; Digital circuit; Jitter; SFQ; Superconductive circuits

Indexed keywords

BIT ERROR RATE; COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; DATA STORAGE EQUIPMENT; DIGITAL INTEGRATED CIRCUITS; JITTER; LOGIC GATES; MICROPROCESSOR CHIPS; PERSONAL COMPUTERS; PROBABILITY; TIMING JITTER; TRIGGER CIRCUITS;

CLOCK GENERATORS; SINGLE FLUX QUANTUM (SFQ); SUPERCONDUCTIVE CIRCUITS; SYSTEM ERROR RATE;

LSI CIRCUITS;

EID: 22144498812     PISSN: 10518223     EISSN: None     Source Type: Journal    
DOI: 10.1109/TASC.2005.849866     Document Type: Conference Paper

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