Trellis-based systolic multi-layer stereo matching

IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation

Volumn 2003-January, Issue , 2003, Pages 257-262

  Jeong, Hong ^a   Park, Sung Chan ^a  

^a Pohang University of Science and Technology (POSTECH)   (South Korea)

Author keywords

Application specific integrated circuits; Bandwidth; Calibration; Frequency; Hardware; Image sequences; Pixel; Real time systems; Stereo vision; Systolic arrays

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; BANDWIDTH; CALIBRATION; COMPUTER HARDWARE; COMPUTER VISION; HARDWARE; IMAGE PROCESSING; INTERACTIVE COMPUTER SYSTEMS; PIXELS; REAL TIME SYSTEMS; SIGNAL PROCESSING; STEREO IMAGE PROCESSING; STEREO VISION; SYSTOLIC ARRAYS;

FREQUENCY; HARDWARE ARCHITECTURE; HIGH-FREQUENCY BANDWIDTH; IMAGE SEQUENCE; LINEAR SYSTOLIC ARRAYS; SELF-CALIBRATION METHOD; STEREO VISION ALGORITHMS; VIDEO IMAGE SEQUENCES;

IMAGE MATCHING;

EID: 21944441816     PISSN: 15206130     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SIPS.2003.1235679     Document Type: Conference Paper

References (5)

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