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Volumn 901, Issue , 1995, Pages 165-184

Automatic correctness proof of the implementation of synchronous sequential circuits using an algebraic approach

Author keywords

[No Author keywords available]

Indexed keywords

ALGEBRA; DESIGN; RECONFIGURABLE HARDWARE; SEQUENTIAL CIRCUITS; SPECIFICATIONS; SWITCHING CIRCUITS; THEOREM PROVING;

EID: 21844484805     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-59047-1_48     Document Type: Conference Paper
Times cited : (5)

References (18)
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    • (1972) Machine Intelligence , Issue.7 , pp. 91-99
    • Cooper, D.C.1
  • 5
    • 0007694967 scopus 로고
    • HOL: A Proof Generating System for Higher Order Logic
    • G. Birtwistle and P. A. Subrahmanyam ed-s., Kluwer Academic Publishers
    • M. J. C. Gordon: "HOL: A Proof Generating System for Higher Order Logic", in VLSI Specification, Verification and Synthesis, G. Birtwistle and P. A. Subrahmanyam ed-s., Kluwer Academic Publishers, pp.73-128, 1988.
    • (1988) VLSI Specification, Verification and Synthesis , pp. 73-128
    • Gordon, M.1
  • 8
    • 0003568839 scopus 로고
    • IEEE Standard VHDL Language Reference Manual
    • IEEE
    • IEEE: "IEEE Standard VHDL Language Reference Manual", IEEE,1988.
    • (1988)
  • 10
    • 27844495205 scopus 로고
    • Principles of Algebraic Language ASL/*
    • July, (in Japanese)
    • T. Kasami, K. Taniguchi, Y. Sugiyama and H. Seki: "Principles of Algebraic Language ASL/*", Trans. of IECE Japan, Vol.69-D, No.7, pp.1066-1074, July 1986 (in Japanese).
    • (1986) Trans. Of IECE Japan , vol.69-D , Issue.7 , pp. 1066-1074
    • Kasami, T.1    Taniguchi, K.2    Sugiyama, Y.3    Seki, H.4
  • 11
    • 84959035433 scopus 로고
    • Top-Down Design Method for Synchronous Sequential Logic Circuits Based on Algebraic Technique
    • March, (in Japanese)
    • J. Kitamiti, T. Higashino, K. Taniguchi and Y. Sugiyama: "Top-Down Design Method for Synchronous Sequential Logic Circuits Based on Algebraic Technique", Trans. of IEICE Japan, Vol.77-A, No.3, March 1994 (in Japanese).
    • (1994) Trans. Of IEICE Japan , vol.77-A , Issue.3
    • Kitamiti, J.1    Higashino, T.2    Taniguchi, K.3    Sugiyama, Y.4
  • 13
    • 0023349316 scopus 로고
    • An Integrated Logic Design Environment Based on Behavioral Description
    • May
    • Y. Nakamura: "An Integrated Logic Design Environment Based on Behavioral Description", IEEE Trans. on Computer-Aided Design Integrated Circuits & Systems, Vol. 6, No. 3, pp.322-336, May 1987.
    • (1987) IEEE Trans. On Computer-Aided Design Integrated Circuits &Systems , vol.6 , Issue.3 , pp. 322-336
    • Nakamura, Y.1
  • 16
    • 84959035435 scopus 로고
    • Using the Language LUSTRE for Sequentiai Circuit Verification
    • North-Holland
    • G. Thuau, B. Berkane, "Using the Language LUSTRE for Sequentiai Circuit Verification", Designing Correct Circuits, North-Holland, pp.81-96~ 1992.
    • (1992) Designing Correct Circuits , pp. 81-96
    • Thuau, G.1    Berkane, B.2
  • 17
    • 84959035436 scopus 로고
    • Open Verilog International: "Verilog Hardware Description Language Reference Manual"
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    • (1991)


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.