Performance and reliability of the multistage bus network

Proceedings of the International Conference on Parallel Processing

Volumn 1, Issue , 1994, Pages

  Bhuyan, Laxmi ^a   Nanda, Ashwini ^b   Askar, Tahsin ^a  

^a TEXAS A AND M UNIVERSITY   (United States)

^b TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIDIRECTIONAL NATURE; INTERMEDIATE STAGE; MULTIPLE STAGES; MULTISTAGE INTERCONNECTION NETWORK; PACKET-SWITCHED; PERFORMANCE ANALYSIS; PERFORMANCE AND RELIABILITIES; SELF-ROUTING;

BUSES;

EID: 21844453994     PISSN: 01903918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICPP.1994.158     Document Type: Conference Paper

References (12)

1. A. W. Wilson, "Hierarchical cache/bus architecture for shared memory multiprocessors", Proc. 14th Ann. Int'l. Symp. on Comp. Arch., pp. 244-252, 1987.
2. E. Hagersten et al., "DDM - a cache only memory architecture", IEEE Computer, pp. 44-54, Sept. 1992.
3. L. N. Bhuyan, Qing Yang, and D. P. Agrawal, "Performance of multiprocessor interconnection networks", IEEE Computer, vol. 22, no. 2, pp. 25-37, Feb. 1989.
4. "Butterfly GP1000 Overview", BBN Advanced Computers, Inc., Nov. 1988.
5. A. Gottlieb et al., "The NYU ultracomputer - Designing an MIMD shared memory parallel computer", IEEE Trans. on Comput., vol. C-32, no. 2, pp. 175-189, Feb. 1983. (Pubitemid 13525125)
6. G. F. Pfister et al., "The IBM research parallel processor prototype (RP3): introduction and architecture", Proc. 1985 Int'l Conf. on Parallel Processing, pp. 764-771, 1985.
7. L. N. Bhuyan and A. K. Nanda, "Multistage bus network(MBN): An interconnection network for cache coherent multiprocessors", Proc. 3rd IEEE Symp, on Parallel and Distributed Processing, pp. 780-787, Dec. 1991.
8. A. K. Nanda and L. N. Bhuyan, "Design and analysis of cache coherent multistage interconnection networks", IEEE Trans, on Computers, pp. 458-470, April 1993.
9. D. H. Lawrie, "Access and alignment of data in an array processor", IEEE Trans, on Comput., vol. C-24, pp. 1145-1155, Dec. 1975.
10. L. N. Bhuyan and D. P. Agrawal, "Design and Performance of Generalized Interconnection Networks", pp. 1081-1090, 1983.
11. L. Kleinrock, Queueing System Vol I: Theory, Wiley & Sons, Inc., New York, 1975.
12. V.P. Kumar and S.M. Reddy, "Augmented shuffle-exchange multistage interconnection networks", IEEE Computer, pp. 30-40, June 1987.