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Volumn 1304, Issue , 1997, Pages 472-481

FPGA implementation of real-time digital controllers using on-line arithmetic

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EID: 21744447683     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-63465-7_253     Document Type: Conference Paper
Times cited : (6)

References (10)
  • 2
    • 0026122037 scopus 로고
    • Module to perform multiplication, division and square root in systolic arrays for matrix computations
    • M.D. Ercegovac and T. Lang, “Module to perform multiplication, division and square root in systolic arrays for matrix computations”, Journal of Parallel and Distributed Computing, vol. 11, pp. 212-221, 1991.
    • (1991) Journal of Parallel and Distributed Computing , vol.11 , pp. 212-221
    • Ercegovac, M.D.1    Lang, T.2
  • 5
    • 0017516220 scopus 로고
    • On-line algorithms for division and multiplication
    • M.D. Ercegovac and K.S. Trivedi, “On-line algorithms for division and multiplication”, IEEE Trans. Comp., vol. C-26, no. 7, pp. 681-687, 1977.
    • (1977) IEEE Trans. Comp , vol.C-26 , Issue.7 , pp. 681-687
    • Ercegovac, M.D.1    Trivedi, K.S.2
  • 6
    • 0018320902 scopus 로고
    • On-line algorithms for the design of pipeline architecture
    • IEEE Computer Society Press
    • M.J. Irwin and R.M. Owens, “On-line algorithms for the design of pipeline architecture”, in 4th Symposium on Computer Architecture. 1979, IEEE Computer Society Press.
    • (1979) 4Th Symposium on Computer Architecture
    • Irwin, M.J.1    Owens, R.M.2
  • 7
    • 84937078021 scopus 로고
    • Signed-digit number representations for fast parallel arithmetic
    • Reprinted in E.E. Swartzlander, Computer Arithmetic, IEEE Computer Society Press Tutorial, 1990
    • A. Avizienis, “Signed-digit number representations for fast parallel arithmetic”, IRE Transactions on Electronic Computers, vol. 10, pp. 389-400, 1961, Reprinted in E.E. Swartzlander, Computer Arithmetic, Vol. 2, IEEE Computer Society Press Tutorial, 1990.
    • (1961) IRE Transactions on Electronic Computers , vol.10-2 , pp. 389-400
    • Avizienis, A.1
  • 8
    • 0030106028 scopus 로고    scopus 로고
    • Reconfigurable logic: Hardware speed with software flexibility
    • July
    • Doug Conner, “Reconfigurable logic: Hardware speed with software flexibility”, EDN Europe, pp. 15-23, July 1996.
    • (1996) EDN Europe , pp. 15-23
    • Conner, D.1
  • 9
    • 0023385902 scopus 로고
    • On-the-fiy conversion of redundant into conventional representations
    • July
    • M.D. Ercegovac and T. Lang, “On-the-fiy conversion of redundant into conventional representations”, IEEE Transactions on Computers, vol. C-36, no. 17, pp. 895-897, July 1987.
    • (1987) IEEE Transactions on Computers , vol.C-36 , Issue.17 , pp. 895-897
    • Ercegovac, M.D.1    Lang, T.2
  • 10


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.