An efficient asic implementation of SHA-1 engine for TPM

IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Volumn 2, Issue , 2004, Pages 873-876

  Ming Yan, Yu ^a   Tong, Zhou ^a   Jin Xiang, Wang ^a   Yi Zheng, Ye ^a  

^a HARBIN INSTITUTE OF TECHNOLOGY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER HARDWARE; COMPUTER SIMULATION; CRYPTOGRAPHY; OPTIMIZATION; SEARCH ENGINES;

CADENCE INC. (CO); PADDING BLOCKS; TRUSTED COMPUTING GROUP (TCG); TRUSTED PLATFORM MODULE (TPM);

VLSI CIRCUITS;

EID: 21644474998     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. TPM Main Part 1 Design Principles, Trusted Computing Group TPM Specification Version 1.2, October 2003.
2. SHA-1 Standard, National Institute of Standards and Technology Secure Hash Standard, Federal Information Processing Standards Publication 180-1, 1995.
3. W. Stallings, Cryptography and Network Security Principles and Practices, Third Edition, NJ: Prentice Hall, 2002, pp. 265-271.
4. K. Martin, Digital Integrated Circuit Design, New York: Oxford University Press, 2001, pp. 412-415.
5. Diez J. M. et al, "Hash Algorithms for Cryptographic Protocols: FPGA Implementations", presented at the 10th Telecommunications forum(TELEFOR'2002), Belgrade, Yugoslavia, 2002.
6. S. Dominikus, "A Hardware Implementation of MD4-Family Hash Algorithms", in proc. of 2002 IEEE International Conference on Electronics Circuits and Systems, Croatia, 2002, Vol. III, pp. 1143-1146.
7. Yong Kyu Kang et al, "An efficient implementation of hash function processor for IPSEC", in proc. of 2002 IEEE Asia-Pacific conference on ASIC, 2002, pp. 93-96.