Digital hardware implementation of a neural network used for classification

Proceedings of the International Conference on Microelectronics, ICM

Volumn , Issue , 2004, Pages 551-554

  Faiedh, Hassène ^a   Gafsi, Zièd ^a   Torki, Kholdoun ^b   Besbes, Kamel ^a  

^a FACULTÉ DES SCIENCES DE MONASTIR   (Tunisia)

^b TIMA LABORATORY   (France)

Author keywords

Artificial neural networks; Digital hardware implementation

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COMPUTER SOFTWARE; DATA COMMUNICATION SYSTEMS; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; MULTILAYERS; SYNCHRONIZATION;

ARTIFICIAL NEURONS; DIGITAL HARDWARE IMPLEMENTATION; ELECTRONIC IMPLEMENTATIONS; NEURON ACTIVATION FUNCTIONS;

NEURAL NETWORKS;

EID: 21644463686     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

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2. th International Conference on Microelectronics, Rabat, Morocco, October 29-31, 2001: 189-192.
3. Bhatnagar H. Advanced ASIC chip synthesis. Kluwer Academic Publishers, London, 2000.
4. Smith Michael JS. Application-specific Integrated Circuits. Addison-Wesley VLSI systems Series, 1999.
5. Sehmid A, Leblebici Y. Mlyuek D. Mixed analogue-digital artificial-neural-network with on chip learning. Circuits, Devices and Systems. IEE Proceedings, 1999; 146(6): 345-349.
6. Hérault J, Jutten C. Réseaux neuronaux et traitement du signal, Hermés, Paris, 1994.