Efficient high-speed quasi-cyclic LDPC decoder architecture

Conference Record - Asilomar Conference on Signals, Systems and Computers

Volumn 1, Issue , 2004, Pages 540-544

  Zhang, Yuping ^a   Wang, Zhongfeng ^b   Parhi, Keshab K ^a  

^a University of Minnesota   (United States)

^b Oregon State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; ALGORITHMS; COMPUTATIONAL COMPLEXITY; COMPUTER HARDWARE; COMPUTER SIMULATION; CRITICAL PATH ANALYSIS; MATHEMATICAL MODELS; TREES (MATHEMATICS); TURBO CODES;

BELIEF PROPAGATION (BP) ALGORITHMS; CHECK NODE FUNCTIONAL UNITS (CNFU); VARIABLE NODE FUNCTIONAL UNITS (VNFU); WIRE INTERCONNECTIONS;

DECODING;

EID: 21644459790     PISSN: 10586393     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. D. Sridhara, T. Fuja, and R. M. Tanner, "Low density parity check codes from permutation matrices," Conf. on Info. Sciences and Systems, The John Hopkins University, March 2001.
2. L. Chen, J. Xun, I. Djurdjevic and Shu Lin, etc, "Near Shannon Limit Quasi-cyclic Low Density Parity-Check Codes," submitted to IEEE Trans. on Communications, 2003.
3. D. Hocevar, "LDPC code construction with flexible hardware implementation," in Proc. IEEE ICC, 2003.
4. D. J. C. Mackay, "Good error correcting codes based on very sparse matrices," IEEE Trans. Inform. Theory, vol. 45, pp. 399-431, March 1999.
5. T. Zhang and K. K. Parhi, "A 54 MBPS (3, 6)-regular FPGA LDPC decoder," in Proc. IEEE SIPS, pp. 127-132, 2002.
6. A. J. Blanksby and C. J. Rowland, "A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity- check code decoder" IEEE J. Solid-State Circuits, vol. 37, pp. 404-412, 2002.
7. Y. Chen and K. K. Parhi, "High throughput overlapped message passing for low density parity check codes," in Proc. IEEE/ACM GLSVLSI, pp. 245-248, 2003.
8. Z. Wang, Y. Chen and K. K. Parhi, "Area efficient decoding of quasi-cyclic low density parity check codes," in Proc.IEEE ICASPP, 2004.