Impact of transistor-to-grain size statistics on large-grain polysilicon TFT characteristics

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2004, Pages 789-790

  Cheng, C F ^a   Poon, M C ^a   Kok, C W ^a   Chan, Mansun ^a  

^a HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

CARRIER MOBILITY; COMPUTER SIMULATION; CRYSTALLIZATION; CURRENT VOLTAGE CHARACTERISTICS; GRAIN BOUNDARIES; GRAIN SIZE AND SHAPE; MATHEMATICAL MODELS; OPTIMIZATION; POLYSILICON; PROBABILITY DISTRIBUTIONS; RELIABILITY; TRANSISTORS;

CRYSTALLIZATION MODELS; GRAIN ENHANCEMENT TECHNOLOGY; METAL-INDUCED-LATERAL CRYSTALLIZATION (MILC); PROBABILISTIC MODELS;

THIN FILM TRANSISTORS; GRAIN SIZE AND SHAPE;

GRAIN BOUNDARY DISTRIBUTION; GRAINSIZE; HIGH MOBILITY; HIGH-LOW; LARGE-GRAIN; MODEL OPTIMIZATION; MODEL-BASED OPC; PERFORMANCE VARIATIONS; TRANSISTOR PERFORMANCE; TRANSISTOR VARIATION;

EID: 21644456202     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)

1. H. Wang, et. al., IEEE TED, vol. 47, pp. 1580-1580, Aug. 2000.
2. A. W. Wang, et. al., IEEE IEDM, pp.277-280, Dec. 1998.