Low leakage reliability characterization methodology for advanced CMOS with gate oxide in the 1nm range

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2004, Pages 477-480

  Chung, Steve S ^a   Feng, H J ^a   Hsieh, Y S ^b   Liu, Alex ^b   Lin, W M ^b   Chen, D F ^b   Ho, J H ^b   Huang, K T ^b   Yang, C K ^b   Cheng, Osbert ^b   Sheng, Y C ^b   Wu, D Y ^b   Shiau, W T ^b   Chien, S C ^b   Liao, Kuan ^b   Sun, S W ^b  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b UNITED MICROELECTRONICS CORPORATION   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

COMMUNICATION CHANNELS (INFORMATION THEORY); ELECTRIC CHARGE; INTERFACES (COMPUTER); LEAKAGE CURRENTS; LOGIC GATES; NATURAL FREQUENCIES; RELIABILITY THEORY; ALUMINUM NITRIDE; CMOS INTEGRATED CIRCUITS; GATES (TRANSISTOR); MOS DEVICES; QUALITY CONTROL; RELIABILITY;

CURRENT ANALYSIS; GATE OXIDE; LEAKAGE CHARACTERIZATION; OXIDE TRAPS;

CMOS INTEGRATED CIRCUITS; MOSFET DEVICES;

ADVANCED CMOS; CHARACTERIZATION TECHNIQUES; CMOS DEVICES; GATE OXIDE; INTERFACE TRAPS; LEAKAGE CHARACTERIZATION; LOW LEAKAGE; NEUTRALISATION; OXIDE TRAPS; RELIABILITY CHARACTERIZATION;

EID: 21644432897     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

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