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Volumn 3, Issue 2, 2003, Pages 127-141

Moore's law and the economics of semiconductor price trends

Author keywords

Industrial organisation; Innovation; Prices; R D; Semiconductors

Indexed keywords

COSTS; ELECTRONICS INDUSTRY; INDUSTRIAL ECONOMICS; INTEGRATED CIRCUITS; JOB ANALYSIS; PRODUCTIVITY; RESEARCH AND DEVELOPMENT MANAGEMENT;

EID: 2142813007     PISSN: 14684322     EISSN: None     Source Type: Journal    
DOI: 10.1504/IJTPM.2003.003885     Document Type: Article
Times cited : (12)

References (37)
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    • note
    • I am grateful for useful conversations about some of the ideas in this paper with Alan Allen, Denis Fandel, Dale Jorgenson, Paul Landler, Bill Spencer, and Phillip Webre. Responsibility for the errors is mine alone.
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    • note
    • Moore [7] notes that the silicon wafers then in use were "usually an inch or more in diameter,' with 'ample room for such a structure if the components can be closely packed with no space wasted for interconnection". He notes that this density "can be achieved by present optical techniques and does not require the more exotic techniques, such as electron beam operations, which are being studied to make even smaller structures".
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    • note
    • For a more comprehensive discussion of IC manufacturing and cost structures, see [11].
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    • Flamm, K. (1993) 'Measurement of DRAM prices: technology and market structure', in Foss, M.F. Manser, M.E. and Young, A.H. (Ed.) Price Measurements and Their Uses, Chicago, University of Chicago Press.
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    • note
    • Over the 1983-1998 period, one estimate is that overall wafer processing cost per square centimeter of silicon increased at a compound annual growth rate of 5.5%. See [13].
  • 13
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    • 29 February. Note that this estimate is per total silicon area processed, not cost per good yielded area. Since good yielded area appears to have increased over time as a fraction of total wafer area processed, with improved processing yields, it seems safe to assume that wafer processing cost per good, yielded silicon area was roughly constant over time.
    • Cunningham, C., Fandel, D., Landler, P. and Wright, R. (2000) 'Silicon productivity trends,' International SEMATECH Technology Transfer No. 00013875A-ENG, 29 February, p.5. Note that this estimate is per total silicon area processed, not cost per good yielded area. Since good yielded area appears to have increased over time as a fraction of total wafer area processed, with improved processing yields, it seems safe to assume that wafer processing cost per good, yielded silicon area was roughly constant over time.
    • (2000) International SEMATECH Technology Transfer No. 00013875A-ENG , pp. 5
    • Cunningham, C.1    Fandel, D.2    Landler, P.3    Wright, R.4
  • 14
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    • note
    • For solid evidence that DRAM yields have increased steadily over time, for successive generations of DRAMs, see [15,160].
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  • 19
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    • note
    • One calculates a factor of 1.37 based on chip area for first versions of six generations of DRAMs. The increase in size is calculated from the data shown in Figure 6.2 in Prince [20, p.209] A similar estimate is implicit in Cunningham et al. [13, p.11] who estimate that area/bit has fallen at a rate of 29% annually over a long period. That works out to an increase in chip size of 41 % with every three-year quadrupling in bits per DRAM.
  • 21
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    • note
    • I.e. chip size increased by about 1.4 rather than 2, for about a 30% reduction in chip size relative to that predicted by lithography alone.
  • 22
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    • note
    • The methodology used for producing the price indexes cited in Flamm [171 takes weighted averages of 'matched model' DRAM chip market prices from one period to the next, with the weights calculated from market revenue shares for each model according to the so-called 'Fisher ideal' index number formula. It does not use any information on price per bit or any other direct calculation of price per electronic element or function. Interestingly, though not a perfect correlation, the Fisher ideal price index and a simple calculation of average price per aggregate bit shipped for all generations of chips produced at any moment are a close match over time. See Flamm ([23] pp.10, 238-239).
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    • note
    • The existence of the National Cooperative Research Act of 1984, which granted partial antitrust exemption to registered US R&D consortia - like SEMATECH, the operational home for the US roadmap - undoubtedly played an important role in making this roadmap coordination process feasible for the industry.
  • 34
    • 2142696177 scopus 로고    scopus 로고
    • note
    • It is claimed that prior to its internationalisation, the SEMATECH membership never accounted for less than 75% of US semiconductor industry sales [29, p.197].
  • 36
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    • They may be accessed through a link found at the
    • They may be accessed through a link found at the International SEMATECH web site, at www.sematech.org.
    • International SEMATECH Web Site
  • 37
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    • note
    • According to the 2000 International Technology Roadmap.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.