A Hierarchical N-Queen Decimation Lattice and Hardware Architecture for Motion Estimation

IEEE Transactions on Circuits and Systems for Video Technology

Volumn 14, Issue 4, 2004, Pages 429-440

  Wang, Chung Neng ^a   Yang, Shin Wei ^a,b   Liu, Chi Min ^a   Chiang, Tihao ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b INSTITUTE FOR INFORMATION INDUSTRY   (Taiwan)

Author keywords

Decimation lattice; Fast motion estimation; Hierarchical decimation lattice; N Queen pattern; Pixel decimation; Video coding

Indexed keywords

ADAPTIVE ALGORITHMS; COMPUTATIONAL COMPLEXITY; DATA STORAGE EQUIPMENT; ELECTRIC DISTORTION; IMAGE CODING; IMAGE QUALITY; MOTION COMPENSATION;

DECIMATION LATTICE; FAST MOTION ESTIMATION; HIERARCHICAL DECIMATION LATTICE; N-QUEEN PATTERN; PIXEL DECIMATION;

MOTION ESTIMATION;

EID: 2142771823     PISSN: 10518215     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSVT.2004.825550     Document Type: Article

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