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Volumn 84, Issue 2, 2004, Pages 197-207
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How to avoid the generation of logic loops in the construction of fault trees
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Author keywords
Fault tree; Hazard Operability analysis; Loop reduction; Recursive operability analysis
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Indexed keywords
ERROR ANALYSIS;
FAILURE ANALYSIS;
MATHEMATICAL MODELS;
PROBABILITY;
SENSORS;
TREES (MATHEMATICS);
HAZARD OPERABILITY ANALYSIS;
LOGIC LOOPS;
LOOP REDUCTION;
RECURSIVE OPERABILITY ANALYSIS;
FAULT TREE ANALYSIS;
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EID: 2142762993
PISSN: 09518320
EISSN: None
Source Type: Journal
DOI: 10.1016/S0951-8320(03)00141-8 Document Type: Article |
Times cited : (19)
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References (13)
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