메뉴 건너뛰기




Volumn 1067, Issue , 1996, Pages 454-459

A parallel genetic algorithm for automatic generation of test sequences for digital circuits

Author keywords

[No Author keywords available]

Indexed keywords

GENETIC ALGORITHMS; TIMING CIRCUITS;

EID: 21344474535     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-61142-8_583     Document Type: Conference Paper
Times cited : (2)

References (11)
  • 3
    • 0027632531 scopus 로고
    • Redundancy Identification/Removal and Test Generation for Sequential Circuits Using Implicit State Enumeration
    • H. Cho, G.D. Hatchel, F. Somenzi, "Redundancy Identification/Removal and Test Generation for Sequential Circuits Using Implicit State Enumeration," IEEE Trans. on CAD/ICAS, Vol. CAD-12, No. 7, pp. 935-945, 1993
    • (1993) IEEE Trans. On CAD/ICAS , vol.CAD-12 , Issue.7 , pp. 935-945
    • Cho, H.1    Hatchel, G.D.2    Somenzi, F.3
  • 8
    • 0008128895 scopus 로고
    • An Automatic Test Pattern Generator for Large Sequential Circuits based on Genetic Algorithms
    • P. Prinetto, M. Rebaudengo, M. Sonza Reorda, "An Automatic Test Pattern Generator for Large Sequential Circuits based on Genetic Algorithms," Proc. Int. Test Conf., 1994, pp. 240-249
    • (1994) Proc. Int. Test Conf. , pp. 240-249
    • Prinetto, P.1    Rebaudengo, M.2    Reorda, M.S.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.