-
1
-
-
0038496831
-
An auto-input-offset removing floating gate pseudo-differential transconductor
-
May
-
T. Constandinou, J. Georgiou, and C. Toumazou, "An auto-input-offset removing floating gate pseudo-differential transconductor," in IEEE Int. Symp. Circuits Systems, May 2003, vol. 1, pp. 169-172.
-
(2003)
IEEE Int. Symp. Circuits Systems
, vol.1
, pp. 169-172
-
-
Constandinou, T.1
Georgiou, J.2
Toumazou, C.3
-
2
-
-
4344714344
-
Fully differential floating-gate programmable OTAs with novel common-mode feedback
-
May
-
R. Chawla, G. Serrano, D. Allen, A. Pereira, and P. Hasler, "Fully differential floating-gate programmable OTAs with novel common-mode feedback," in IEEE Int. Symp. Circuits Systems, May 2004, vol. 1, pp. I-817-820.
-
(2004)
IEEE Int. Symp. Circuits Systems
, vol.1
-
-
Chawla, R.1
Serrano, G.2
Allen, D.3
Pereira, A.4
Hasler, P.5
-
3
-
-
0036977193
-
A floating-gate vector-quantizer
-
Aug.
-
P. Hasler, P. Smith, C. Duffy, C. Gordon, J. Dugger, and D. Anderson, "A floating-gate vector-quantizer," in Proc. IEEE Midwest Symp. Circuits and Syst, Aug. 2002, vol. 1, pp. I-196-199.
-
(2002)
Proc. IEEE Midwest Symp. Circuits and Syst
, vol.1
-
-
Hasler, P.1
Smith, P.2
Duffy, C.3
Gordon, C.4
Dugger, J.5
Anderson, D.6
-
4
-
-
0035052016
-
An autozeroing floating-gate amplifier
-
P. Hasler, D. Minch, and C. Diorio, "An autozeroing floating-gate amplifier," IEEE Trans. Circuits Syst. II, vol. 48, no. 1, pp. 74-82, 2001.
-
(2001)
IEEE Trans. Circuits Syst. II
, vol.48
, Issue.1
, pp. 74-82
-
-
Hasler, P.1
Minch, D.2
Diorio, C.3
-
5
-
-
0038529372
-
A 300-MS/s 14-bit digital-to-analog converter in logic CMOS
-
J. Hyde, T. Humes, C. Diorio, M. Thomas, and M. Figueroa, "A 300-MS/s 14-bit digital-to-analog converter in logic CMOS," IEEE J. Solid-State Circuits, vol. 38, no. 5, pp. 734-740, 2003.
-
(2003)
IEEE J. Solid-State Circuits
, vol.38
, Issue.5
, pp. 734-740
-
-
Hyde, J.1
Humes, T.2
Diorio, C.3
Thomas, M.4
Figueroa, M.5
-
6
-
-
0016961262
-
On-chip high-voltage generation in NMOS integrated circuits using an improved voltage multiplier technique
-
J. Dickson, "On-chip high-voltage generation in NMOS integrated circuits using an improved voltage multiplier technique," IEEE J. Solid-State Circuits, vol. 11, no. 3, pp. 374-378, 1976.
-
(1976)
IEEE J. Solid-state Circuits
, vol.11
, Issue.3
, pp. 374-378
-
-
Dickson, J.1
-
7
-
-
2342635094
-
An ultra-low-power digitally-controlled buck converter 1C for cellular phone applications
-
J. Xiao, A. Peterchev, J. Zhang, and S. Sanders, "An ultra-low-power digitally-controlled buck converter 1C for cellular phone applications," in Proc. IEEE Appl. Power Electron. Conf., 2004, vol. 1, pp. 383-391.
-
(2004)
Proc. IEEE Appl. Power Electron. Conf.
, vol.1
, pp. 383-391
-
-
Xiao, J.1
Peterchev, A.2
Zhang, J.3
Sanders, S.4
-
9
-
-
0035043074
-
Programming floating-gate circuits with UV-activated conductances
-
Y. Berg, T.S. Lande, and Ø. Næss, "Programming floating-gate circuits with UV-activated conductances," IEEE Trans. Circuits Syst. II, vol. 48, no. 1, pp. 12-19, 2001.
-
(2001)
IEEE Trans. Circuits Syst. II
, vol.48
, Issue.1
, pp. 12-19
-
-
Berg, Y.1
Lande, T.S.2
Næss, Ø.3
-
10
-
-
0027719698
-
An associative memory integrated system for character recognition
-
Aug.
-
P. Pouliquen, A. Andreou, K. Strohbehn, and R. Jenkins, "An associative memory integrated system for character recognition," in Proc. IEEE Midwest Symp. Circuits and Syst, Aug. 1993, vol. 1, pp. 762-765.
-
(1993)
Proc. IEEE Midwest Symp. Circuits and Syst
, vol.1
, pp. 762-765
-
-
Pouliquen, P.1
Andreou, A.2
Strohbehn, K.3
Jenkins, R.4
-
11
-
-
34250901737
-
A heteroassociative memory using current-mode MOS analog VLSI circuits
-
K. Boahen, P. Pouliquen, A. Andreou, and R. Jenkins, "A heteroassociative memory using current-mode MOS analog VLSI circuits," IEEE Trans. Circuits Syst., vol. 36, no. 5, pp. 747-755, 1989.
-
(1989)
IEEE Trans. Circuits Syst.
, vol.36
, Issue.5
, pp. 747-755
-
-
Boahen, K.1
Pouliquen, P.2
Andreou, A.3
Jenkins, R.4
-
12
-
-
0036470223
-
VLSI implementation of fuzzy adaptive resonance and learning vector quantizalion
-
J. Lubkin and G. Cauwenberghs, "VLSI implementation of fuzzy adaptive resonance and learning vector quantizalion,"Int. J. Analog Integrated Circuits and Signal Processing, vol. 30, no. 2, pp. 149-157, 2002.
-
(2002)
Int. J. Analog Integrated Circuits and Signal Processing
, vol.30
, Issue.2
, pp. 149-157
-
-
Lubkin, J.1
Cauwenberghs, G.2
-
13
-
-
0024891252
-
Analog VLSI synaptic matrices as building blocks for neural networks
-
O. Rossetto, C. Jutten, J. Herault, and I. Kreuzer, "Analog VLSI synaptic matrices as building blocks for neural networks," IEEE Micro, vol. 9, no. 6, pp. 56-63, 1989.
-
(1989)
IEEE Micro
, vol.9
, Issue.6
, pp. 56-63
-
-
Rossetto, O.1
Jutten, C.2
Herault, J.3
Kreuzer, I.4
-
14
-
-
0026866246
-
Current-mode subthreshold MOS implementation of the Herault-Jutten autoadaptive network
-
M. Cohen and A. Andreou, "Current-mode subthreshold MOS implementation of the Herault-Jutten autoadaptive network," IEEE J. Solid-State Circuits, vol. 27, no. 5, pp. 714-727, 1992.
-
(1992)
IEEE J. Solid-state Circuits
, vol.27
, Issue.5
, pp. 714-727
-
-
Cohen, M.1
Andreou, A.2
-
15
-
-
0035046840
-
Correlation learning rule in floating-gate pFET synapses
-
P. Hasler and J. Dugger, "Correlation learning rule in floating-gate pFET synapses," IEEE Trans. Circuits Syst. II, vol. 48, no. 1, pp. 65-73, 2001.
-
(2001)
IEEE Trans. Circuits Syst. II
, vol.48
, Issue.1
, pp. 65-73
-
-
Hasler, P.1
Dugger, J.2
-
16
-
-
0035051734
-
Continuous-time feedback in floating-gate MOS circuits
-
January
-
P. Hasler, "Continuous-time feedback in floating-gate MOS circuits," IEEE Trans. Circuits Syst. II, vol. 48, no. 1, pp. 56-64, January 2001.
-
(2001)
IEEE Trans. Circuits Syst. II
, vol.48
, Issue.1
, pp. 56-64
-
-
Hasler, P.1
-
17
-
-
0036294819
-
A simulation model for floating-gate MOS synapse transistors
-
May
-
K. Rahimi, C. Diorio, C. Hernandez., and M. Brockhausen, "A simulation model for floating-gate MOS synapse transistors," in IEEE Int. Symp. Circuits Systems, May 2002, vol. 2, pp. 532-535.
-
(2002)
IEEE Int. Symp. Circuits Systems
, vol.2
, pp. 532-535
-
-
Rahimi, K.1
Diorio, C.2
Hernandez, C.3
Brockhausen, M.4
-
18
-
-
0026257527
-
Effect of hot-carrier injection on n- And pMOSFET gate oxide integrity
-
K. Rosenbaum, R. Rofan, and C. Hu, "Effect of hot-carrier injection on n- and pMOSFET gate oxide integrity," IEEE Electron Device Letters, vol. 12, no. 11, pp. 599-601, 1991.
-
(1991)
IEEE Electron Device Letters
, vol.12
, Issue.11
, pp. 599-601
-
-
Rosenbaum, K.1
Rofan, R.2
Hu, C.3
-
19
-
-
4143073663
-
Effect of hot-carrier injection on n- And pMOSFET gate oxide integrity
-
B. Kaczar, R. Degraeve, G. Groeseneken, M. Rasras, S. Kubicek, E. Vandamme, and G. Badenes, "Effect of hot-carrier injection on n- and pMOSFET gate oxide integrity," in IEDM Technical Digest, 2000, pp. 553-556.
-
(2000)
IEDM Technical Digest
, pp. 553-556
-
-
Kaczar, B.1
Degraeve, R.2
Groeseneken, G.3
Rasras, M.4
Kubicek, S.5
Vandamme, E.6
Badenes, G.7
-
20
-
-
0242526854
-
Analog soft-pattern-matching classifier using floating-gate MOS technology
-
T. Yamasaki and T. Shibata, "Analog soft-pattern-matching classifier using floating-gate MOS technology," IEEE Trans. Neural Networks, vol. 14, no. 5, pp. 1257-1265, 2003.
-
(2003)
IEEE Trans. Neural Networks
, vol.14
, Issue.5
, pp. 1257-1265
-
-
Yamasaki, T.1
Shibata, T.2
-
21
-
-
4344606658
-
Adaptive log domain filters using floating gate transistors
-
May
-
P. Abshire, E. Wong, Y. Zhai, and M. Cohen, "Adaptive log domain filters using floating gate transistors," in IEEE Int. Symp. Circuits Systems, May 2004, vol. 1, pp. I-29-32.
-
(2004)
IEEE Int. Symp. Circuits Systems
, vol.1
-
-
Abshire, P.1
Wong, E.2
Zhai, Y.3
Cohen, M.4
-
22
-
-
0033326071
-
AdOpt: Analog VLSI stochastic optimization for adaptive optics
-
July, vol. lxii+4439
-
M. Cohen, R. Edwards, G. Cauwenberghs, M. Vorontsov, and G. Carhart, "AdOpt: Analog VLSI stochastic optimization for adaptive optics," in Int. Joint Conf. Neural Networks, July 1999, vol. lxii+4439, pp. 762-765.
-
(1999)
Int. Joint Conf. Neural Networks
, pp. 762-765
-
-
Cohen, M.1
Edwards, R.2
Cauwenberghs, G.3
Vorontsov, M.4
Carhart, G.5
-
23
-
-
0035051733
-
A CMOS programmable analog memory-cell array using floating-gate circuits
-
R. Harrison, J. Bragg, P. Hasler, B. Minch, and S. Deweerth, "A CMOS programmable analog memory-cell array using floating-gate circuits," IEEE Trans. Circuits Syst. II, vol. 48, no. 1, pp. 4-11, 2001.
-
(2001)
IEEE Trans. Circuits Syst. II
, vol.48
, Issue.1
, pp. 4-11
-
-
Harrison, R.1
Bragg, J.2
Hasler, P.3
Minch, B.4
Deweerth, S.5
-
24
-
-
4344575838
-
5 V-only, standard 5 μm CMOS programmable and adaptive floating-gate circuits and arrays using CMOS charge pumps
-
May
-
M. Hooper, M. Kucic, and P. Hasler, "5 V-only, standard 5 μm CMOS programmable and adaptive floating-gate circuits and arrays using CMOS charge pumps," in IEEE Int. Symp. Circuits Systems, May 2004, vol. 5, pp. 832-835.
-
(2004)
IEEE Int. Symp. Circuits Systems
, vol.5
, pp. 832-835
-
-
Hooper, M.1
Kucic, M.2
Hasler, P.3
-
25
-
-
34547980583
-
A 1.2 GHz adaptive floating gate comparator with 13-bit resolution
-
to appear in, May
-
E. Wong, P. Abshire, and M. Cohen, "A 1.2 GHz adaptive floating gate comparator with 13-bit resolution," to appear in IEEE Int. Symp. Circuits Systems, May 2005.
-
(2005)
IEEE Int. Symp. Circuits Systems
-
-
Wong, E.1
Abshire, P.2
Cohen, M.3
-
26
-
-
0026996006
-
Design techniques for high-speed, high-resolution comparators
-
D. Razavi and B. Wooley, "Design techniques for high-speed, high-resolution comparators," IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 1916-1926, 1992.
-
(1992)
IEEE J. Solid-state Circuits
, vol.27
, Issue.12
, pp. 1916-1926
-
-
Razavi, D.1
Wooley, B.2
-
27
-
-
0035043140
-
Hoating-gate adaptation for focal-plane online nonuniformity correction
-
M. Cohen and G. Cauwenberghs, "Hoating-gate adaptation for focal-plane online nonuniformity correction," IEEE Trans. Circuits Syst. II, vol. 48, no. 1, pp. 83-89, 2001.
-
(2001)
IEEE Trans. Circuits Syst. II
, vol.48
, Issue.1
, pp. 83-89
-
-
Cohen, M.1
Cauwenberghs, G.2
-
28
-
-
0036290585
-
A temperature independent trimmable current source
-
May
-
S. Shah and S. Collins, "A temperature independent trimmable current source," in IEEE Int. Symp. Circuits Systems, May 2002, vol. 1, pp. 1713-1716.
-
(2002)
IEEE Int. Symp. Circuits Systems
, vol.1
, pp. 1713-1716
-
-
Shah, S.1
Collins, S.2
-
29
-
-
0035051604
-
A programmable current mirror for analog trimming using single poly floating-gate devices in standard CMOS technology
-
S. Jackson, J. Killens, and B. Blalock, "A programmable current mirror for analog trimming using single poly floating-gate devices in standard CMOS technology," IEEE Trans. Circuits Syst. II, vol. 48, no. 1, pp. 100-102, 2001.
-
(2001)
IEEE Trans. Circuits Syst. II
, vol.48
, Issue.1
, pp. 100-102
-
-
Jackson, S.1
Killens, J.2
Blalock, B.3
-
30
-
-
84922849140
-
Comments on 'an optimized output stage for MOS integrated circuits'
-
R. Jaeger, "Comments on 'An optimized output stage for MOS integrated circuits'," IEEE J. Solid-State Circuits, vol. SC-10, no. 1, pp. 185-186, 1975.
-
(1975)
IEEE J. Solid-state Circuits
, vol.SC-10
, Issue.1
, pp. 185-186
-
-
Jaeger, R.1
-
31
-
-
0035696160
-
A 6-b 1.3-Gsample/s A/D converter in 0.35 μm CMOS
-
M. Choi and A. Abidi, "A 6-b 1.3-Gsample/s A/D converter in 0.35 μm CMOS," IEEE J. Solid-State Circuits, vol. 36, no. 12, pp. 1847-1858, 2001.
-
(2001)
IEEE J. Solid-state Circuits
, vol.36
, Issue.12
, pp. 1847-1858
-
-
Choi, M.1
Abidi, A.2
-
32
-
-
0003476558
-
-
Piscataway, NJ, Wiley-IEEE Press
-
R.J. Baker, H.W. Li, and D.H. Boyce, CMOS Circuit Design, Layout, and Simulation. Piscataway, NJ, Wiley-IEEE Press, 1997.
-
(1997)
CMOS Circuit Design, Layout, and Simulation
-
-
Baker, R.J.1
Li, H.W.2
Boyce, D.H.3
|