A scalable embedded DSP core for SoC applications

2004 International Symposium on System-on-Chip Proceedings

Volumn , Issue , 2004, Pages 85-88

  Panis, C ^a   Hirnschrott, U ^b   Farfeleder, S ^b   Krall, A ^b   Laure, G ^c   Lazian, W ^c   Nurmi, J ^d  

^a Carinthian Tech Institute   (Austria)

^b VIENNA UNIVERSITY OF TECHNOLOGY   (Austria)

^c INFINEON TECHNOLOGIES AUSTRIA AG   (Austria)

^d TAMPERE UNIVERSITY OF TECHNOLOGY   (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL ALGORITHMS; HIGH VOLUME PRODUCTS; PROGRAMMABLE CORES; SILICON AREA;

COMPUTER ARCHITECTURE; COMPUTER HARDWARE; EMBEDDED SYSTEMS; ENERGY DISSIPATION; INTEGRATED CIRCUIT LAYOUT; PROBLEM SOLVING; PRODUCT DEVELOPMENT; PROGRAM COMPILERS; SPECIFICATIONS;

ELECTRONICS PACKAGING;

EID: 21244499770     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)

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2. "Blackfin DSP Instruction Set Reference", Digital Signal Processor Division, Analog Devices Inc., First Revision, March 2002.
3. "Lisa 2.0 Language Reference Manual, Manual RM_2002.02", LisaTek, February 2002.
4. "The ArchC Architecture Description Language v0.8.1, Reference Manual", www.archc.org, 2004.
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6. P. Lapsley, J. Bier, A. Shoham and E.A. Lee, DSP Processor Fundamentals, Architectures and Features, IEEE Press, New York, 1997.
7. C. Panis, R. Leitner, H. Grünbacher, J. Nurmi, "xLIW - a Scaleable Long Instruction Word", in Proc. The 2003 IEEE International Symposium on Circuits and Systems (ISCAS 2003), Bangkok, Thailand, May 25-28, 2003, pp. V69-V72
8. C. Panis, U. Hirnschrott, A. Krall, G. Laure, W. Lazian, J. Nurmi, "FSEL - Selective Predicated Execution for a Configurable DSP Core", in Proceedings of IEEE Annual Symposium on VLSI (ISVLSI-04), Lafayette, Louisiana, USA, February 19-20, 2004, pp. 317-320.
9. D. Sima, T. Fountain, P. Kacsuk, Advanced Computer Architectures: A Design Space Approach, Addison Wesley Publishing Company, Harlow, 1997.
10. "An Introduction to Thumb", Advanced RISC Machines Ltd., Version 2.0, March 1995.
11. C. Panis, "Scalable DSP Core Architecture Addressing Compiler Requirements", PhD thesis at Tampere University of Technology, Tampere, Finland, August 2004.