A reconfigurable FPU as IP component for SoCs

2004 International Symposium on System-on-Chip Proceedings

Volumn , Issue , 2004, Pages 103-106

  Brunelli, Claudio ^a   Campi, Fabio ^b   Kylliäinen, Juha ^a   Nurmi, Jari ^a  

^a TAMPERE UNIVERSITY OF TECHNOLOGY   (Finland)

^b UNIVERSITY OF BOLOGNA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL COMPLEXITY; COMPUTER SOFTWARE REUSABILITY; COSTS; INTELLECTUAL PROPERTY; MARKETING; MICROELECTRONICS; STANDARDS;

COPROCESSORS; FLOATING-POINT UNIT; IMAGE ELABORATION; SYSTEM ON CHIP DESIGN;

INTEGRATED CIRCUIT LAYOUT;

EID: 21244494025     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

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