-
1
-
-
0034843014
-
VSIPL: An object-based open standard API for vector, signal, and image processing
-
J. Lebak, R. Janka, R. Judd, M. Richards, and D. Campbell, "VSIPL: An object-based open standard API for vector, signal, and image processing," in Proc. 2001 IEEE Int. Conf. Acoustics, Speech, and Signal Processing, vol. 2, pp. 949-952.
-
Proc. 2001 IEEE Int. Conf. Acoustics, Speech, and Signal Processing
, vol.2
, pp. 949-952
-
-
Lebak, J.1
Janka, R.2
Judd, R.3
Richards, M.4
Campbell, D.5
-
2
-
-
84860949970
-
Vector, Signal, and Image Processing Library (VSIPL) 1.0 application programmer's interface
-
[Online]
-
D. A. Schwartz, R. R. Judd, W. J. Harrod, and D. P. Manley. (2000) Vector, Signal, and Image Processing Library (VSIPL) 1.0 application programmer's interface. Georgia Tech Res. Corp. [Online], Available: http://www.vsipl.org
-
(2000)
Georgia Tech Res. Corp.
-
-
Schwartz, D.A.1
Judd, R.R.2
Harrod, W.J.3
Manley, D.P.4
-
3
-
-
84901784702
-
A portable object-based parallel library and layered framework for real-time radar signal processing
-
C. M. DeLuca, C. W. Heisey, R. A. Bond, and J. M. Daly, "A portable object-based parallel library and layered framework for real-time radar signal processing," in Proc. 1st Conf. International Scientific Computing in Object-Oriented Parallel Environments (ISCOPE '97), pp. 241-248.
-
Proc. 1st Conf. International Scientific Computing in Object-Oriented Parallel Environments (ISCOPE '97)
, pp. 241-248
-
-
Deluca, C.M.1
Heisey, C.W.2
Bond, R.A.3
Daly, J.M.4
-
4
-
-
20744443122
-
Achieving portable task and data parallelism on signal processing architectures
-
Lexington, MA
-
H. Hoffmann, J. Daly, J. Matlis, P. Richardson, E. Rutledge, and G. Schrader, "Achieving portable task and data parallelism on signal processing architectures," presented at the 4th Annu. High-Performance Embedded Computing (HPEC) Workshop, Lexington, MA, 2000.
-
(2000)
4th Annu. High-Performance Embedded Computing (HPEC) Workshop
-
-
Hoffmann, H.1
Daly, J.2
Matlis, J.3
Richardson, P.4
Rutledge, E.5
Schrader, G.6
-
5
-
-
0003253871
-
Easy expression templates using PETE, the portable expression template engine
-
Oct.
-
S. Haney, J. Crotinger, S. Karmesin, and S. Smith, "Easy expression templates using PETE, the portable expression template engine," Dr. Dobb's J., pp. 88-95, Oct. 1999.
-
(1999)
Dr. Dobb's J.
, pp. 88-95
-
-
Haney, S.1
Crotinger, J.2
Karmesin, S.3
Smith, S.4
-
6
-
-
0012416708
-
Rapid application development and enhanced code interoperability using the POOMA framework
-
Yorktown Heights, NY
-
J. C. Cummings, J. A. Crotinger, S. W. Haney, W. F. Humphrey, S. R. Karmesin, J. V. Reynders, S. A. Smith, and T. J. Williams, "Rapid application development and enhanced code interoperability using the POOMA framework," presented at the SIAM Workshop Object-Oriented Methods and Code Interoperability in Scientific and Engineering Computing (OO'98), Yorktown Heights, NY.
-
SIAM Workshop Object-Oriented Methods and Code Interoperability in Scientific and Engineering Computing (OO'98)
-
-
Cummings, J.C.1
Crotinger, J.A.2
Haney, S.W.3
Humphrey, W.F.4
Karmesin, S.R.5
Reynders, J.V.6
Smith, S.A.7
Williams, T.J.8
-
7
-
-
20744453937
-
Preliminary design review: Narrowband GMTI processing for the basic PCA radar-tracker application
-
MIT Lincoln Lab., Lexington, MA
-
A. I. Reuther, "Preliminary design review: Narrowband GMTI processing for the basic PCA radar-tracker application," MIT Lincoln Lab., Lexington, MA, Project Rep. PCA-IRT-3, 2003.
-
(2003)
Project Rep.
, vol.PCA-IRT-3
-
-
Reuther, A.I.1
-
8
-
-
20744442097
-
Missile seeker common computer signal processing architecture for rapid technology upgrade
-
Lexington, MA
-
D. Rabinkin, E. Rutledge, and P. Monticciolo, "Missile seeker common computer signal processing architecture for rapid technology upgrade," presented at the 6th Annu. High-Performance Embedded Computing (HPEC) Workshop, Lexington, MA, 2002.
-
(2002)
6th Annu. High-Performance Embedded Computing (HPEC) Workshop
-
-
Rabinkin, D.1
Rutledge, E.2
Monticciolo, P.3
-
9
-
-
15844370130
-
Missile seeker common computer architecture for rapid technology upgrade
-
Jul.
-
_, "Missile seeker common computer architecture for rapid technology upgrade," Proc. SPIE, Advanced Signal Processing Algorithms, Architectures, and Implementations XIV, vol. 5559, pp. 131-145, Jul. 2004.
-
(2004)
Proc. SPIE, Advanced Signal Processing Algorithms, Architectures, and Implementations XIV
, vol.5559
, pp. 131-145
-
-
-
11
-
-
20744436780
-
Continuous real-time signal processing: Comparing the tigerSHARC and the powerPC
-
Dec.
-
J. Mirod, "Continuous real-time signal processing: Comparing the tigerSHARC and the powerPC," COTS J., no. 12, pp. 32-37, Dec. 2002.
-
(2002)
COTS J.
, Issue.12
, pp. 32-37
-
-
Mirod, J.1
-
12
-
-
20744442685
-
COTS software portability standards and VSIPL benchmarks
-
Lexington, MA
-
R. Teachey, A. Donadeo, E. Pancoast, G. Faix, and B. Chin, "COTS software portability standards and VSIPL benchmarks," presented at the 4th Annu. High-Performance Embedded Computing (HPEC) Workshop, Lexington, MA, 2000.
-
(2000)
4th Annu. High-Performance Embedded Computing (HPEC) Workshop
-
-
Teachey, R.1
Donadeo, A.2
Pancoast, E.3
Faix, G.4
Chin, B.5
-
13
-
-
20744448340
-
Successful VSIPL software application migration - A case study: NATO Seasparrow illumination radar signal processing
-
Lexington, MA
-
D. Averill, "Successful VSIPL software application migration - A case study: NATO Seasparrow illumination radar signal processing," presented at the 7th Annu. High-Performance Embedded Computing (HPEC) Workshop, Lexington, MA, 2003.
-
(2003)
7th Annu. High-Performance Embedded Computing (HPEC) Workshop
-
-
Averill, D.1
-
17
-
-
0001981541
-
Expression templates
-
T. Veldhuizen, "Expression templates," C++ Rep., vol. 7, no. 5, pp. 26-31, 1995.
-
(1995)
C++ Rep.
, vol.7
, Issue.5
, pp. 26-31
-
-
Veldhuizen, T.1
-
18
-
-
0348226755
-
Efficient implementation of a portable parallel programming model for image processing
-
P. J. Morrow, D. Crookes, J. Brown, G. Mcaleese, D. Roantree, and I. Spence, "Efficient implementation of a portable parallel programming model for image processing," Concurrency Pract. Exper., vol. 11, no. 11, pp. 671-685, 1999.
-
(1999)
Concurrency Pract. Exper.
, vol.11
, Issue.11
, pp. 671-685
-
-
Morrow, P.J.1
Crookes, D.2
Brown, J.3
Mcaleese, G.4
Roantree, D.5
Spence, I.6
-
19
-
-
19344368072
-
SPIRAL: Code generation for DSP transforms
-
Feb.
-
M. Puschel, J. M. F. Moura, J. Johnson, D. Padua, M. Veloso, B. W. Singer, J. Xiong, F. Franchetti, A. Gačić, Y. Voronenko, K. Chen, R. W. Johnson, and N. Rizzolo, "SPIRAL: Code generation for DSP transforms," Proc. IEEE, vol. 93, no. 2, pp. 232-275, Feb. 2005.
-
(2005)
Proc. IEEE
, vol.93
, Issue.2
, pp. 232-275
-
-
Puschel, M.1
Moura, J.M.F.2
Johnson, J.3
Padua, D.4
Veloso, M.5
Singer, B.W.6
Xiong, J.7
Franchetti, F.8
Gačić, A.9
Voronenko, Y.10
Chen, K.11
Johnson, R.W.12
Rizzolo, N.13
-
20
-
-
0141496142
-
Learning to construct fast signal processing implementations
-
B. Singer and M. Veloso, "Learning to construct fast signal processing implementations," J. Mach. Learn. Res., vol. 3, pp. 887-919, 2002.
-
(2002)
J. Mach. Learn. Res.
, vol.3
, pp. 887-919
-
-
Singer, B.1
Veloso, M.2
-
21
-
-
20744449792
-
The design and implementation of FFTW3
-
Feb.
-
M. Frigo and S. G. Johnson, "The design and implementation of FFTW3," Proc. IEEE, vol. 93, no. 2, pp. 216-231, Feb. 2005.
-
(2005)
Proc. IEEE
, vol.93
, Issue.2
, pp. 216-231
-
-
Frigo, M.1
Johnson, S.G.2
-
22
-
-
20744452904
-
Self adapting linear algebra algorithms and software
-
Feb.
-
J. Demmel, J. Dongarra, V. Eijkhout, E. Fuentes, A. Petitet, R. Vuduc, C. Whaley, and K. Yelick, "Self adapting linear algebra algorithms and software," Proc. IEEE, vol. 93, no. 2, pp. 293-312, Feb. 2005.
-
(2005)
Proc. IEEE
, vol.93
, Issue.2
, pp. 293-312
-
-
Demmel, J.1
Dongarra, J.2
Eijkhout, V.3
Fuentes, E.4
Petitet, A.5
Vuduc, R.6
Whaley, C.7
Yelick, K.8
-
23
-
-
2342559116
-
User transparency: A fully sequential programming model for efficient data parallel image processing
-
F. Seinstra and D. Koelma, "User transparency: A fully sequential programming model for efficient data parallel image processing," Concurrency Comput. Pract. Exper., vol. 16, no. 7, 2004.
-
(2004)
Concurrency Comput. Pract. Exper.
, vol.16
, Issue.7
-
-
Seinstra, F.1
Koelma, D.2
-
24
-
-
84948606064
-
Automatic mapping of large signal processing systems to a parallel machine
-
Aug.
-
H. Printz, H. Kung, T. Mummert, and P. Scherer, "Automatic mapping of large signal processing systems to a parallel machine," Proc. SPIE, Real-Time Signal Processing XII, vol. 1154, pp. 2-16, Aug. 1989.
-
(1989)
Proc. SPIE, Real-Time Signal Processing XII
, vol.1154
, pp. 2-16
-
-
Printz, H.1
Kung, H.2
Mummert, T.3
Scherer, P.4
-
25
-
-
58749091514
-
A model-integrated program synthesis environment for parallel/real-time image processing
-
Jul.
-
M. S. Moore, J. Sztipanovitz, G. Karsai, and J. Nichols, "A model-integrated program synthesis environment for parallel/real-time image processing," Proc. SPIE, Parallel and Distributed Methods for Image Processing, vol. 3166, pp. 31-45, Jul. 1997.
-
(1997)
Proc. SPIE, Parallel and Distributed Methods for Image Processing
, vol.3166
, pp. 31-45
-
-
Moore, M.S.1
Sztipanovitz, J.2
Karsai, G.3
Nichols, J.4
-
26
-
-
0038070649
-
A toolkit for parallel image processing
-
July
-
J. M. Squyres, A. Lumsdaine, and R. L. Stevenson, "A toolkit for parallel image processing," Proc. SPIE, Parallel and Distributed Methods for Image Processing II, vol. 3452, pp. 69-80, July 1998.
-
(1998)
Proc. SPIE, Parallel and Distributed Methods for Image Processing II
, vol.3452
, pp. 69-80
-
-
Squyres, J.M.1
Lumsdaine, A.2
Stevenson, R.L.3
-
29
-
-
20744438305
-
AltiVec technology programming interface manual
-
"AltiVec technology programming interface manual," Motorola Semiconductor Products, 1999.
-
(1999)
Motorola Semiconductor Products
-
-
-
32
-
-
20744458362
-
VSIPL++/FPGA design methodology
-
Lexington, MA
-
J. Bergmann, S. Emeny, and P. Bronowicz, "VSIPL++/FPGA design methodology," presented at the 7th Annu. High-Performance Embedded Computing (HPEC) Workshop, Lexington, MA, 2003.
-
(2003)
7th Annu. High-Performance Embedded Computing (HPEC) Workshop
-
-
Bergmann, J.1
Emeny, S.2
Bronowicz, P.3
-
34
-
-
0038222919
-
S3P: Automatic, optimized mapping of signal processing applications to parallel architectures
-
Lexington, MA
-
H. Hoffmann, J. V. Kepner, and R. A. Bond, "S3P: Automatic, optimized mapping of signal processing applications to parallel architectures," presented at the 5th Annu. High-Performance Embedded Computing (HPEC) Workshop, Lexington, MA, 2001.
-
(2001)
5th Annu. High-Performance Embedded Computing (HPEC) Workshop
-
-
Hoffmann, H.1
Kepner, J.V.2
Bond, R.A.3
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