Silicon nanocrystals: From coulomb blockade to memory arrays

2004 4th IEEE Conference on Nanotechnology

Volumn , Issue , 2004, Pages 290-292

  Steimle, R F ^a   Rao, R ^a   Sadd, M ^a   Swift, C ^a   Hradsky, B ^a   Straub, S ^a   Merchant, T ^a   Stoker, M ^a   Parikh, C ^a   Anderson, S ^a   Rossow, M ^a   Yater, J ^a   Acred, B ^a   Harber, K ^a   Prinz, E ^a   White Jr , B E ^a   Muralidhar, R ^a  

^a MOTOROLA INC   (United States)

Author keywords

MOS memory integrated circuits; Nanotechnology; Semiconductor device fabrication; Semiconductor materials; Semiconductor memories

Indexed keywords

COULOMB BLOCKADE; FABRICATION; MOS DEVICES; NANOTECHNOLOGY; NUCLEATION; PROBLEM SOLVING; SEMICONDUCTOR MATERIALS; SEMICONDUCTOR STORAGE; SILICON; THRESHOLD VOLTAGE;

MOS MEMORY INTEGRATED CIRCUITS; SEMICONDUCTOR DEVICE FABRICATION; SEMICONDUCTOR MEMORIES; SILICON NANOCRYSTALS;

NANOSTRUCTURED MATERIALS;

EID: 20344379225     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. S. Tiwari, et al. IEDM Technical Digest, 20.4.1, 1995
2. T. Kamins, "Polycrystalline Silicon for Integrated Circuits and Displays," Kluwer Academic Publishers, Massachusetts, (1998).
3. K.C. Scheer et al., J. Appl. Phys., 93, 5637, (2003).
4. M. Sadd, et al., Proceedings of the IEEE Non Volatile Semiconductor Memory Workshop, 2001
5. Boaz Eitan, Intl. Conf. Solid State Dev. Matls, Japan, 1999.
6. B. Hradsky et al, IEEE Non-Volatile Memory Workshop 2003