Fabrication of N+/P ultra-shallow junctions by plasma doping for 65 nm CMOS technology

Surface and Coatings Technology

Volumn 186, Issue 1-2 SPEC. ISS., 2004, Pages 17-20

  Lallement, Fabrice ^a   Grouillet, A ^a   Juhel, M ^a   Reynard, J P ^a   Lenoble, D ^a   Fang, Z ^b   Walther, S ^b   Rault, Y ^b   Godet, L ^b   Scheuer, J ^b  

^a STMICROELECTRONICS   (France)

^b VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES   (United States)

Author keywords

65 nm CMOS technology; Design Of Experiment (DOE); Junction depth; N+ P ultra shallow junction; Plasma doping; Sheet resistance

Indexed keywords

ANNEALING; CMOS INTEGRATED CIRCUITS; OPTIMIZATION; SEMICONDUCTOR DEVICES; SEMICONDUCTOR JUNCTIONS;

DESIGN OF EXPERIMENT (DOE); PLASMA DOPING (PLAD); PLASMA-DOPED WAFERS; ULTRA-SHALLOW JUNCTIONS (USJ);

PLASMA DEVICES;

PLASMA TREATMENT;

EID: 20244389408     PISSN: 02578972     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.surfcoat.2004.04.004     Document Type: Article

References (5)

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4. Pouydebasque A et al. Proceedings of ESSDERC, Lisbon, Portugal 2003
5. Lenoble D et al. Proceedings of IIT Conference, Taos, NM, USA 2002