Ge deep sub-micron pFETs with etched TaN metal gate on a High-K dielectric, fabricated in a 200mm silicon prototyping line

ESSCIRC 2004 - Proceedings of the 34th European Solid-State Device Research Conference

Volumn , Issue , 2004, Pages 189-192

  De Jaeger, B ^a   Houssa, M ^a   Satta, A ^a   Kubicek, S ^a   Verheyen, P ^a,e   Van Steenbergen, J ^a   Croon, J ^a   Kaczer, B ^a   Van Elshocht, S ^a   Delabie, A ^a   Kunnen, E ^a   Sleeckx, E ^a   Teerlinck, I ^a   Lindsay, R ^a   Schram, T ^a   Chiarella, T ^a   Degraeve, R ^a   Conard, T ^a   Poortmans, J ^a   Winderickx, G ^a   Boullart, W ^a   Schaekers, M ^a   Mertens, P W ^a   Caymax, M ^a   Vandervorst, W ^a   Van Moorhem, E ^a   Biesemans, S ^a   De Meyer, K ^a,e   Ragnarsson, L ^a   Lee, S ^b   Kota, G ^b   Raskin, G ^c   Mijlemans, P ^c   Autran, J L ^d   Afanas'ev, V ^e   Stesmans, A ^e   Meuris, M ^a   Heyns, M ^a   more..

^a IMEC   (Belgium)

^b LAM RESEARCH CORPORATION   (United States)

^c UMICORE   (Belgium)

^d AIX MARSEILLE UNIVERSITÉ   (France)

^e UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DEPOSITION; DIELECTRIC MATERIALS; ELECTRONS; ETCHING; TITANIUM NITRIDE; ULSI CIRCUITS;

GATE STACK; INTERFACE STATES; METAL GATES; SILICON PROTOTYPING LINE;

GATES (TRANSISTOR);

EID: 20244383594     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. Chui, C.O. et al., IEDM'02, p.437
2. Shang, H. et al., IEDM'02, p.441
3. Huang, C.H. et al., VLSI'03, p.119
4. Appleton, B.R. et al., Appl.Phys. Lett.41, p711,1982
5. Holland, O.W. et al., J. Appl. Phys. 54, p.2295, 1983
6. Bai, W.P. et al., VLSI'03, p.121
7. Shang, H. et al., IEEE Electron Dev. Lett. 24, p242, 2003