DC and RF characterization of fully depleted strained SOI MOSFETs

Proceedings - IEEE International SOI Conference

Volumn , Issue , 2004, Pages 86-88

  Chen, C L ^a   Langdo, T A ^b   Chen, C K ^a   Fiorenza, J G ^b   Wyatt, P W ^a   Currie, M T ^b   Leitz, C W ^b   Braithwaite, G ^b   Fritze, M ^a   Lambert, R ^a   Yost, D R ^a   Cheng, Z ^b   Lochtefeld, A ^b   Keast, C K ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^b AmberWave Systems Corporation   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BURIED OXIDE (BOX); GATE LENGTH; GATE RESISTANCE; WAFER BONDING;

CMOS INTEGRATED CIRCUITS; LEAKAGE CURRENTS; OPTIMIZATION; SEMICONDUCTING SILICON; SILICON ON INSULATOR TECHNOLOGY; THRESHOLD VOLTAGE; TRANSCONDUCTANCE;

MOSFET DEVICES;

EID: 20144387359     PISSN: 1078621X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

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4. C.K. Chen et al., SOI Conf. Dig., 2003, pp. 39-40.
5. C.L. Chen et al., IEEE Elect. Dev. Letts, vol.23, 2002, pp. 52-54.
6. S. Takagi et al., IEDM Tech Dig., 2003, pp. 57-60.
7. S. Y. Chou et al., IEEE Trans Elect Dev, vol. ED-34, 1987, pp. 448-50.