A threshold logic-based reconfigurable logic element with a new programming technology

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1896, Issue , 2000, Pages 665-674

  Aoyama, Kazuo ^a   Sawada, Hiroshi ^a   Nagoya, Akira ^b   Nakajima, Kazuo ^c  

^a Nippon Telegraph and Telephone Corporation   (Japan)

^b NTT Corporation   (Japan)

^c UNIVERSITY OF MARYLAND   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT SIMULATION; DIGITAL STORAGE; RECONFIGURABLE ARCHITECTURES; THRESHOLD LOGIC;

MEMORY CIRCUITS; NEURON MOS TRANSISTORS; PROGRAMMING TECHNOLOGY; RECONFIGURABLE; RECONFIGURABLE LOGIC; SYMMETRIC FUNCTIONS; THRESHOLD GATES; VARIABLE THRESHOLDS;

RECONFIGURABLE HARDWARE;

EID: 20044362663     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-44614-1_71     Document Type: Conference Paper

References (6)

1. Brown, S.D., Francis, R.J., Rose, J., Vranesic, Z.G.: Field-Programmable Gate Arrays. Kluwer Academic Publishers (1992)
2. Shibata, T., Ohmi, T.: A Functional MOS Transistor Featuring Gate-Level Weighted Sum and Threshold Operations. IEEE Trans. ED. 39 (1992) 1444-1455
3. Shibata, T., Kotani, K., Ohmi, T.: Real-Time Reconfigurable Logic Circuits Using Neuron MOS Transistors. IEEE ISSCC93 FA 15.3 (1993) 238-239
4. Shibata, T., Ohmi, T.: Neuron MOS Binary-Logic Integrated Circuits-Part I: Design Fundamentals and Soft-Hardware-Logic Circuit Implementation. IEEE Trans. ED. 40 (1993) 570-576
5. Shibata, T., Ohmi, T.: Neuron MOS Binary-Logic Integrated Circuits-Part II: Simplifying Techniques of Circuit Configuration and their Practical Applications. IEEE Trans. ED. 40 (1993) 974-979
6. Muroga, S.: Threshold Logic and Its Applications. John Wiley & Sons, Inc. (1971)