Ultra-thin strained SOI substrate analysis by pseudo-MOS measurements

Microelectronic Engineering

Volumn 80, Issue SUPPL., 2005, Pages 241-244

  Gallon, C ^a,c   Fenouillet Beranger, C ^b   Bresson, N ^c,d   Cristoloveanu, S ^c   Allibert, F ^d   Bord, S ^a   Aulnette, C ^d   Delille, D ^e   Latu Romain, E ^f,g   Hartmann, J M ^b   Ernst, T ^b   Andrieu, F ^b,c   Campidelli, Y ^a   Ghyselen, B ^d   Cayrefourcq, I ^d   Fournel, F ^b   Kernevez, N ^b   Skotnicki, T ^a  

^a STMICROELECTRONICS   (France)

^b CEA LETI   (France)

^c IMEP LAHC   (France)

^d PARC TECHNOLOGIQUE DES FONTAINES   (France)

^e PHILIPS RESEARCH LABORATORIES   (Germany)

^f FREESCALE SEMICONDUCTOR INC   (United States)

^g LEPMI   (France)

Author keywords

Pseudo MOS measurements; Ultra thin Strained SOI

Indexed keywords

CAPACITANCE; CARRIER MOBILITY; CMOS INTEGRATED CIRCUITS; INTERFACES (MATERIALS); MOS DEVICES; SILICON WAFERS; THIN FILMS; VOLTAGE CONTROL;

MOBILITY REDUCTION; PSEUDO-MOS MEASUREMENTS; SILICON FILMS; ULTRA-THIN STRAINED SOI;

SILICON ON INSULATOR TECHNOLOGY;

EID: 19944366977     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mee.2005.04.074     Document Type: Conference Paper

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