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Volumn 25, Issue 7, 2005, Pages 92-96

New three-level neutral point potential hysteresis-band control

Author keywords

Neutral point balance; Power electronics; Pulse width modulation; Selected harmonic elimination; Three level

Indexed keywords

CONTROL; HYSTERESIS; INSULATED GATE BIPOLAR TRANSISTORS; POWER ELECTRONICS; PULSE WIDTH MODULATION; SWITCHES; VOLTAGE CONTROL;

EID: 19644399253     PISSN: 02588013     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article
Times cited : (36)

References (15)
  • 2
    • 0036686037 scopus 로고    scopus 로고
    • Multilevel inverters: A survey of topologies, controls, and applications
    • Jose Rodriguez, Jih-Sheng Lai, Fang Zheng Peng. Multilevel inverters: a survey of topologies, controls, and applications[J]. IEEE Trans. Industrial Electronics, 2002, 49(4): 724-738.
    • (2002) IEEE Trans. Industrial Electronics , vol.49 , Issue.4 , pp. 724-738
    • Jose, R.1    Lai, J.-S.2    Peng, F.Z.3
  • 3
    • 0033733214 scopus 로고    scopus 로고
    • A comprehensive study of neutral-point voltage balancing problem in three-level neutral-point-clamped voltage source PWM inverters
    • Celanovic N, Boroyevich D. A comprehensive study of neutral-point voltage balancing problem in three-level neutral-point-clamped voltage source PWM inverters [J]. Power Electronics, IEEE Transactions on, Volume: 15, 2000, 15(2): 242-249.
    • (2000) IEEE Transactions on Power Electronics , vol.15 , Issue.2 , pp. 242-249
    • Celanovic, N.1    Boroyevich, D.2
  • 4
    • 1542331720 scopus 로고    scopus 로고
    • Mechanism of dc bus voltage unbalance in diode-clamped multilevel inverters
    • Wang Guangzhu. Mechanism of dc bus voltage unbalance in diode-clamped multilevel inverters [J]. Proceedings of the CSEE, 2002, 22(12): 111-117.
    • (2002) Proceedings of the CSEE , vol.22 , Issue.12 , pp. 111-117
    • Wang, G.1
  • 5
    • 0035519969 scopus 로고    scopus 로고
    • Experimental comparisons of space vector neutral point balancing strategies for three-level topology
    • Zhou Dongsheng, Rouaud D G. Experimental comparisons of space vector neutral point balancing strategies for three-level topology [J]. IEEE Trans. Power Electronics, 2001, 16(6): 872-879.
    • (2001) IEEE Trans. Power Electronics , vol.16 , Issue.6 , pp. 872-879
    • Zhou, D.1    Rouaud, D.G.2
  • 6
    • 0036875735 scopus 로고    scopus 로고
    • A self-balancing space vector switching modulator for three-level motor drives
    • Zhou Dongsheng. A self-balancing space vector switching modulator for three-level motor drives [J]. IEEE Trans. Power Electronics, 2002, 17(6): 1024-1031.
    • (2002) IEEE Trans. Power Electronics , vol.17 , Issue.6 , pp. 1024-1031
    • Zhou, D.1
  • 7
    • 1442303230 scopus 로고    scopus 로고
    • A three-level PWM method of neutral-point balancing and narrow-pulse elimination
    • Jin Shun, Zhong Yanru, Ming Zhengfeng et al. A three-level PWM method of neutral-point balancing and narrow-pulse elimination [J]. Proceedings of the CSEE, 2003, 23(10): 114-118.
    • (2003) Proceedings of the CSEE , vol.23 , Issue.10 , pp. 114-118
    • Jin, S.1    Zhong, Y.2    Ming, Z.3
  • 8
    • 0036756743 scopus 로고    scopus 로고
    • Improvement on dc-voltage balance control method of three-level inverter
    • Weng Haiqing, Sun Xudong, Liu Congwei et al. Improvement on dc-voltage balance control method of three-level inverter [J]. Proceedings of the CSEE, 2002, 22(9): 114-118.
    • (2002) Proceedings of the CSEE , vol.22 , Issue.9 , pp. 114-118
    • Weng, H.1    Sun, X.2    Liu, C.3
  • 9
    • 0037230676 scopus 로고    scopus 로고
    • A neutral-point potential balancing algorithm for three-level NPC inverters using analytically injected zero-sequence voltage
    • Song Qiang, Liu Wenhua, Yu Qingguang. A neutral-point potential balancing algorithm for three-level NPC inverters using analytically injected zero-sequence voltage [C]. 2003. APEC '03. Eighteenth Annual IEEE, 2003, 1: 228-233.
    • (2003) APEC'03, Eighteenth Annual IEEE , vol.1 , pp. 228-233
    • Song, Q.1    Liu, W.2    Yu, Q.3
  • 10
    • 0033335551 scopus 로고    scopus 로고
    • A DC-link voltage balancing algorithm for 3-level converter using the zero sequence current
    • Sun-Kyoung Lim, Jun-Ha Kim, Kwanghee Nam. A DC-link voltage balancing algorithm for 3-level converter using the zero sequence current. Power Electronics Specialists Conference [C], 1999. PESC 99. 30th Annual IEEE, 1999, 2: 1083-1088.
    • (1999) Power Electronics Specialists Conference, 30th Annual IEEE , vol.2 , pp. 1083-1088
    • Lim, S.-K.1    Kim, J.-H.2    Nam, K.3
  • 12
    • 1642447012 scopus 로고    scopus 로고
    • Research on selected harmonic elimination applicable to three-level voltage inverters
    • Fei Wanming, Lu Zhengyu, Yao Wenxi. Research on Selected Harmonic Elimination Applicable to Three-level Voltage Inverters [J]. Proceedings of the CSEE, 2003, 23(9): 11-15.
    • (2003) Proceedings of the CSEE , vol.23 , Issue.9 , pp. 11-15
    • Fei, W.1    Lu, Z.2    Yao, W.3
  • 13
    • 2342428158 scopus 로고    scopus 로고
    • Research of selected harmonic elimination PWM technique applicable to multi-level voltage inverters
    • Fei Wanming, Lu Zhengyu, Yao Wenxi. Research of selected harmonic elimination PWM technique applicable to multi-level voltage inverters[J]. Proceedings of the CSEE, 2004, 24(1): 102-106.
    • (2004) Proceedings of the CSEE , vol.24 , Issue.1 , pp. 102-106
    • Fei, W.1    Lu, Z.2    Yao, W.3
  • 14
    • 0036871968 scopus 로고    scopus 로고
    • A method of solution to selective harmonic eliminated PWM switching angles for NPC inverters
    • Liu WenHua, Song Qiang, Chen Yuanhua et al. A method of solution to selective harmonic eliminated PWM switching angles for NPC inverters[J]. Proceedings of the CSEE, 2002, 22(11): 31-34.
    • (2002) Proceedings of the CSEE , vol.22 , Issue.11 , pp. 31-34
    • Liu, W.1    Song, Q.2    Chen, Y.3
  • 15
    • 2342509636 scopus 로고    scopus 로고
    • Three-level SVPWM method based on two-level PWM cell in DSP
    • Yao Wenxi, Lu Zhengyu, Fei Wanmin. Three-level SVPWM method based on two-level PWM cell in DSP [C]. 2004. APEC'04. Nineteenth Annual IEEE, 2004, 3: 1720-1724.
    • (2004) APEC'04. Nineteenth Annual IEEE , vol.3 , pp. 1720-1724
    • Yao, W.1    Lu, Z.2    Fei, W.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.