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Volumn 21, Issue 2, 2004, Pages 102-109

Automatic test program generation: A case study

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SIMULATION; DESIGN FOR TESTABILITY; GENETIC ALGORITHMS; OPTIMIZATION; PIPELINE PROCESSING SYSTEMS;

EID: 1942532276     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2004.1277902     Document Type: Article
Times cited : (116)

References (14)
  • 2
    • 77951139654 scopus 로고    scopus 로고
    • Verifying a simple pipelined microprocessor using maude
    • Springer-Verlag
    • N.A. Harman, "Verifying a Simple Pipelined Microprocessor Using Maude," Lecture Notes in Computer Science 2267, Springer-Verlag, 2001, pp. 128-142.
    • (2000) Lecture Notes in Computer Science 2267 , pp. 128-142
    • Harman, N.A.1
  • 4
    • 0033684177 scopus 로고    scopus 로고
    • Formal verification of superscalar microprocessors with multicycle functional units, exception, and branch prediction
    • ACM Press
    • M.N. Velev and R.E. Bryant, "Formal Verification of Superscalar Microprocessors with Multicycle Functional Units, Exception, and Branch Prediction," Proc. 37th Design Automation Conf. (DAC 00), ACM Press, 2000, pp. 112-117.
    • (2000) Proc. 37th Design Automation Conf. (DAC 00) , pp. 112-117
    • Velev, M.N.1    Bryant, R.E.2
  • 6
    • 0034997102 scopus 로고    scopus 로고
    • Methodology for synthesis, testing, and verification of pipelined architecture processors from behavioral-level-only HDL code and a case study example
    • IEEE Press
    • J. R. Heath and S. Durbha, "Methodology for Synthesis, Testing, and Verification of Pipelined Architecture Processors from Behavioral-Level-Only HDL Code and a Case Study Example," Proc. IEEE Southeast Conf., IEEE Press, 2001, pp. 143-149.
    • (2001) Proc. IEEE Southeast Conf. , pp. 143-149
    • Heath, J.R.1    Durbha, S.2
  • 7
    • 0032306939 scopus 로고    scopus 로고
    • Native mode functional test generation for processors with applications to selt-test and design validation
    • IEEE CS Press
    • J. Shen and J.A. Abraham, "Native Mode Functional Test Generation for Processors with Applications to Selt-Test and Design Validation," Proc. IEEE Int'l Test Conf. (ITC 98), IEEE CS Press, 1998, pp. 990-999.
    • (1998) Proc. IEEE Int'l Test Conf. (ITC 98) , pp. 990-999
    • Shen, J.1    Abraham, J.A.2
  • 8
    • 0142246920 scopus 로고    scopus 로고
    • Application and analysis of RT-level software-based self-testing for embedded processor cores
    • IEEE CS Press
    • N. Kranitis et al., "Application and Analysis of RT-Level Software-Based Self-Testing for Embedded Processor Cores," Proc. Int'l Test Conf., IEEE CS Press, 2003, pp. 431-440.
    • (2003) Proc. Int'l Test Conf. , pp. 431-440
    • Kranitis, N.1
  • 11
    • 1642612182 scopus 로고    scopus 로고
    • Fully automatic test program generation for microprocessor cores
    • IEEE CS Press
    • F. Corno et al., "Fully Automatic Test Program Generation for Microprocessor Cores," Proc. IEEE Design, Automation and Test in Europe (DATE 03), IEEE CS Press, 2003, pp. 1006-1011.
    • (2003) Proc. IEEE Design, Automation and Test in Europe (DATE 03) , pp. 1006-1011
    • Corno, F.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.