A formal semantics for Verilog-VHDL simulation interoperability by abstract state machine

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 1999, Pages 353-357

  Sasaki, Hisashi ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ABSTRACT STATE MACHINES; FORMAL SEMANTICS; SEMANTIC FUNCTIONS; SEMANTIC INTEROPERABILITY; SIMULATION INTEROPERABILITY; SIMULATION MODEL; TIMING CONTROL; VHDL-AMS;

COMPUTER SIMULATION; EXHIBITIONS; INTEROPERABILITY;

SEMANTICS;

EID: 18944390150     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.1999.761145     Document Type: Conference Paper

References (23)

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