A multi-standard video accelerator based on a vector architecture

IEEE Transactions on Consumer Electronics

Volumn 51, Issue 1, 2005, Pages 160-167

  Chouliaras, Vassilios A ^a   Nunez, José Luis ^b   Mulvaney, David J ^a   Rovati, Fabricio S ^c   Alfonso, Daniele ^c  

^a LOUGHBOROUGH UNIVERSITY   (United Kingdom)

^b UNIVERSITY OF BRISTOL   (United Kingdom)

^c STMICROELECTRONICS   (Italy)

Author keywords

Embedded RISC; H264; MPEG2; MPEG4; Vector SIMD accelerator

Indexed keywords

COMPUTATIONAL COMPLEXITY; IMAGE COMPRESSION; IMAGE PROCESSING; MOTION COMPENSATION; MOTION ESTIMATION; STANDARDS; VECTOR QUANTIZATION;

H264; MPEG2; MPEG4; MULTI-STANDARD VIDEO ACCELERATOR; VECTOR ARCHITECTURE; VIDEO CODING STANDARDS;

IMAGE CODING;

EID: 18844382930     PISSN: 00983063     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCE.2005.1405714     Document Type: Article

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