Effect of wafer warpage on leakage yield loss of bipolar transistors

International Symposium on IC Technology, Systems and Applications

Volumn 7, Issue , 1997, Pages 250-253

  Chiou, Herng Der ^a   Yahya, Amir Raslan ^b  

^a MOTOROLA INC   (United States)

^b Motorola Electronics Sdn Bhd   (Malaysia)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR TRANSISTORS; CRYSTALS; CURRENT DENSITY; DEFECTS; FAILURE (MECHANICAL); FAILURE ANALYSIS; LEAKAGE CURRENTS; OXIDATION; OXIDES; OXYGEN; TEMPERATURE;

HIGH OXYGEN CONCENTRATION; LEAKAGE YIELD LOSS; MICRODEFECTS; OXIDE PRECIPITATE NUCLEI; SEED END CRYSTALS; WAFER WARPAGE;

SILICON WAFERS;

EID: 1842780059     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

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