SCOPUS 정보 검색 플랫폼

IEEE Micro

Volumn 24, Issue 1, 2004, Pages 24-31

ETA: Experience with an intel xeon processor as a packet processing engine

(5) Regnier, Greg a Minturn, Dave a McAlpine, Gary a Saletore, Vikram A a Foong, Annie a

a INTEL CORPORATION (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CLIENT SERVER COMPUTER SYSTEMS; GENERAL PURPOSE COMPUTERS; INTERFACES (COMPUTER); INTERNET; MICROPROCESSOR CHIPS; NETWORK PROTOCOLS; PACKET NETWORKS; SOFTWARE PROTOTYPING;

EMBEDDED TRANSPORT ACCELERATION; INTEL XEON PROCESSORS; PACKET PROCESSING ENGINE; SOFTWARE PARTITIONING;

MULTIPROCESSING SYSTEMS;

EID: 1842583301 PISSN: 02721732 EISSN: None Source Type: Journal
DOI: 10.1109/MM.2004.1268989 Document Type: Article

Times cited : (23)

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2
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5
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- Count on TCP offload engines
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6
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- Storage over IP: When does hardware support help?
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- Buonadonna, P.¹ Culler, D.²

8
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- TCP servers: Offloading TCP processing in internet servers
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9
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- A 10GHz TCP offload accelerator for 10Gbps ethernet in 90nm dual-VT CMOS
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- Hoskote, Y.¹

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