An Elastic Pipeline Mechanism by Self-Timed Circuits

IEEE Journal of Solid-State Circuits

Volumn 23, Issue 1, 1988, Pages 111-117

  Komori, Shinji ^a   Takata, Hidehiro ^a   Tamura, Toshiyuki ^a   Asai, Fumiyasu ^a   Ohno, Takio ^a   Tomisawa, Osamu ^a   Yamasaki, Tetsuo ^a   Shima, Kenji ^a   Asada, Katsuhiko ^b   Terada, Hiroaki ^b  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

^b OSAKA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 1842542572     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.266     Document Type: Article

References (5)

1. J. L. Hennessy, “VLSI processor architecture,” IEEE Trans. Computer, vol. C-33, no. 12, pp. 1221–1246, Dec. 1984.
2. H. Nishikawa, H. Terada, K. Komatsu, S. Yoshida, T. Okamoto, Y. Tsuji, S. Takakura, T. Tokura, Y. Nishikawa, S. Hara, and M. Meichi, “Architecture of a one-chip data-driven processor: Q-p,” in Proc. 16th Int. Conf. Parallel Processing, Aug. 1987, pp. 319-326.
3. K. Asada, H. Terada, S. Matsumoto, S. Miyata, H. Asano, H. Miura, M. Shimizu, S. Komori, T. Fukuhara, and K. Shima, “Hardware structure of a one-chip data-driven processor: Q-p,” in Proc. 16th Int. Conf. Parallel Processing, Aug. 1987, pp. 327-329.
4. C. L. Seitz, “System timing,” in Introduction to VLSI Systems, C. Mead, and L. Conway, Eds. Reading, MA: Addison-Wesley 1981, ch. 7.
5. H. Terada, H. Nishikawa, K. Asada, S. Matsumoto, S. Miyata, S. Komori, and K. Shima, “VLSI design of a one-chip data-driven processor: Q-vl,” in Proc. Fall Joint Computer Conf., Oct. 1987, pp. 594–601.