Different Operational Transconductance Amplifier topologies for obtaining very small transconductances

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 4, Issue , 2000, Pages IV-189-IV-192

  Veeravalli, A ^a   Sanchez Sinencio, E ^a   Silva Martinez, J ^a,b  

^a TEXAS A AND M UNIVERSITY   (United States)

^b INSTITUTO NACIONAL DE ASTROFÍSICA   (Mexico)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; ELECTRIC NETWORK TOPOLOGY; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; MOSFET DEVICES; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE MODELS; SIGNAL TO NOISE RATIO; TRANSCONDUCTANCE;

OPERATIONAL TRANSCONDUCTANCE AMPLIFIERS (OTA);

OPERATIONAL AMPLIFIERS;

EID: 18344414490     PISSN: 02714310     EISSN: None     Source Type: Journal    
DOI: 10.1109/ISCAS.2000.858720     Document Type: Article

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