SCALING STUDIES OF CMOS SRAM SOFT-ERROR TOLERANCES - FROM 16K TO 256K.

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 1987, Pages 540-543

  Fu, J S ^a   Lee, K H ^a   Koga, R ^a   Hewlett, F W ^a   Flores, R ^a   Anderson, R E ^a   Desko, J C ^a   Nagy, W J ^a   Shimer, J A ^a   Kohler, R A ^a   Steenwyk, S D ^a  

^a SANDIA NATIONAL LABORATORIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA STORAGE, SEMICONDUCTOR - FABRICATION; SEMICONDUCTOR DEVICES, MOS;

CMOS SRAM; SCALING EFFECTS; SOFT ERROR TOLERANCE; STATIC RAM (SRAM);

DATA STORAGE, DIGITAL;

EID: 18144448640     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)