A comparison by simulation and by measurement of the substrate noise generated by CMOS, CSL, and CBL digital circuits

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 52, Issue 4, 2005, Pages 734-741

  Albuquerque, Edgar Francisco Monteiro ^a   Silva, Manuel Medeiros ^a  

^a INESC ID   (Portugal)

Author keywords

CMOS integrated circuits; Logic families; Low noise logic; Mixed signal integrated circuits; Substrate noise

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; INDUCTANCE; LOGIC CIRCUITS; MATHEMATICAL MODELS; SPURIOUS SIGNAL NOISE; SUBSTRATES;

LOGIC FAMILIES; LOW NOISE LOGIC; MIXED SIGNAL INTEGRATED CIRCUITS; SUBSTRATE NOISE;

DIGITAL CIRCUITS;

EID: 18144421551     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2005.844110     Document Type: Article

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