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Volumn , Issue , 2004, Pages 343-347
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An efficient architecture design for deblocking loop filter
a
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Author keywords
H.264 AVS Deblocking filter Pipelining VLSI
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Indexed keywords
CODES (SYMBOLS);
COMPUTER SIMULATION;
FIR FILTERS;
IMAGE CODING;
INTERFACES (COMPUTER);
LOGIC GATES;
STATIC RANDOM ACCESS STORAGE;
ADVANCED VIDEO CODING (AVC);
H.264 AVS DEBLOCKING FILTER PIPELINING VLSI;
JOINT VIDEO TEAM (JVT);
WRITE BACK (WB) UNIT;
VLSI CIRCUITS;
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EID: 18144407307
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
Times cited : (14)
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References (6)
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