At-speed interconnect test and diagnosis of external memories on a system

Proceedings - International Test Conference

Volumn , Issue , 2004, Pages 156-162

  Kim, Heon C ^a   Jun, Hong Shin ^a   Gu, Xinli ^a   Chung, Sung S ^a  

^a CISCO SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DOUBLE DATA RATE (DDR); FAST CYCLE RAM (FCRAM); IN-CIRCUIT TESTER (ICT); SYSTEM CLOCK;

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; BUILT-IN SELF TEST; MATHEMATICAL MODELS; NETWORK PROTOCOLS; STATIC RANDOM ACCESS STORAGE;

INTEGRATED CIRCUIT TESTING;

EID: 18144390639     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. IEEE Standard Test Access Port and Boundary-Scan Architecture, IEEE std. 1149.1-1990, IEEE Computer Society.
2. Benoit Nadeau-Dostie, Jean-Francois Cote, Harry Hulvershorn, and Stephen Pateras, "An Embedded Technique For At-Speed Interconnect Testing," Proc. International Test Conference, 1999, pp. 431-438.
3. Jongchul Shin, Hyunjin Kim, and Sungho Kang, "At-Speed Boundary-Scan Interconnect Testing," Proc. Design Automation and Test in Europe (DATE), 1999, pp. 473-477.
4. Chen-Huan Chiang, "BIST TPG for SRAM Cluster Interconnect Testing at Board Level," Proc. Asian Test Symposium, 2000, pp. 58-65.
5. Benoit Nadeau-Dostie, "Design for at-speed Test, Diagnosis and Measurement," Kluwer Academic Publishers, Boston, U.S.A.
6. Xinli Gu, Weili Wang, Kevin Li, Heon Kim, and Sung Chung, "Re-Using DFT Logic for Functional and Silicon Debugging Test," Proc. of International Test Conference 2002, pp. 648-656.
7. Oliver Caty, Ismet Bayraktaroglu, Amitava Majumdar, Richard Lee, John Bell, and Lisa Curhan, "Instruction Based BIST for Board/System Level Test of External Memories and Interconnects," Proc. of International Test Conference 2003, pp. 140-149.