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Volumn 14, Issue 4, 2005, Pages 16-20
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Through-wafer via etching
a a a a |
Author keywords
[No Author keywords available]
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Indexed keywords
CHIP SCALE PACKAGES;
CMOS INTEGRATED CIRCUITS;
ELECTRONIC EQUIPMENT MANUFACTURE;
ELECTRONICS PACKAGING;
INDUCTIVELY COUPLED PLASMA;
INPUT OUTPUT PROGRAMS;
MICROELECTROMECHANICAL DEVICES;
MICROMACHINING;
SCANNING ELECTRON MICROSCOPY;
SILICON WAFERS;
BOSCH PROCESS;
CHIP SCALE PACKAGING (CSP);
DEEP REACTIVE ION ETCHING;
MOORE'S LAW;
SYSTEM ON CHIP (SOC);
REACTIVE ION ETCHING;
ETCHING;
PACKAGING;
SCANNING ELECTRON MICROSCOPY;
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EID: 18144372732
PISSN: 10650555
EISSN: None
Source Type: Trade Journal
DOI: None Document Type: Review |
Times cited : (5)
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References (7)
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