C BC reduction in InP heterojunction bipolar transistor with selectively implanted collector pedestal

Device Research Conference - Conference Digest, DRC

Volumn , Issue , 2004, Pages 67-68

  Dong, Yingda ^a   Griffith, Zach ^a   Dahlström, Mattias ^a   Rodwell, Mark J W ^a  

^a Santa Barbara   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BASE-COLLECTOR JUNCTION CAPACITANCE; BASE-COLLECTOR JUNCTION LEAKAGE; COLLECTOR PEDESTRAL; DELTA DOPING;

CAPACITANCE; CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC RESISTANCE; ION IMPLANTATION; LEAKAGE CURRENTS; MOLECULAR BEAM EPITAXY; PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION; SEMICONDUCTING INDIUM GALLIUM ARSENIDE; SEMICONDUCTING INDIUM PHOSPHIDE; SEMICONDUCTOR GROWTH;

HETEROJUNCTION BIPOLAR TRANSISTORS;

EID: 18044370246     PISSN: 15483770     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DRC.2004.1367786     Document Type: Conference Paper

References (3)

1. th IEEE GaAsIC Symposium.
2. Y. Dong, et al, 'InP Heterojunction Bipolar Transistor with a Selectively Implanted Collector Pedestal', Proceedings of 2003 International Semiconductor Device Research Symposium, pp. 348-349, December 10-12, Washington, D.C
3. Y. Dong, et al, 'Compensation of Interfacial Charges at the Regrowth Interface between InP Layers', submitted to Electronic Materials Conference, 2004