A Robust 65-nm Node CMOS Technology for Wide-Range Vdd Operation

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2003, Pages 281-284

  Nakahara, Y ^a   Fukai, T ^b   Togo, M ^b   Koyama, S ^a   Morikuni, H ^a   Matsuda, T ^a   Sakamoto, K ^a   Mineji, A ^a   Fujiwara, S ^a   Kunimune, Y ^a   Nagase, M ^a   Tamura, T ^a   Onoda, N ^a   Miyake, S ^a   Yama, Y ^a   Kudoh, T ^a   Ikeda, M ^a   Yamagata, Y ^a   Yamamoto, T ^b   Imai, K ^a  

^a RENESAS TECHNOLOGY CORP   (Japan)

^b NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE MEASUREMENT; CONCENTRATION (PROCESS); CURRENT VOLTAGE CHARACTERISTICS; DOPING (ADDITIVES); ENERGY DISSIPATION; ION IMPLANTATION; LEAKAGE CURRENTS; MOSFET DEVICES; PARAMETER ESTIMATION; PHOSPHORUS; PRODUCT DESIGN; STRESS ANALYSIS; TEMPERATURE MEASUREMENT; THICKNESS MEASUREMENT; TRANSIENTS; TRANSMISSION ELECTRON MICROSCOPY;

POWER DISSIPATION; TRANSIENT ENHANCED DIFFUSION (TED);

CMOS INTEGRATED CIRCUITS;

EID: 17644439703     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. T. Sakurai, ISSCC Dig., p.26, 2003
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3. Bin Yu et al., Symp. on VLSI Tech., p.9, 2001
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5. T. Fukai et al., Symp. on VLSI Tech., p.83, 2003
6. K. Imai et al., EDM Tech. Dig., p.455, 2000
7. P. S. Lee et al, J. Electrochem. Soc., v.149, p.331, 2002
8. K. Imai et al., EEDM Tech. Dig., p.667, 1999