Floorplan-aware low-complexity digital filter synthesis for low-power & high-speed

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2004, Pages 354-357

  Choo, Hunsoo ^a   Roy, Kaushik ^a  

^a Purdue University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; DIGITAL SIGNAL PROCESSING; GENERAL PURPOSE COMPUTERS; LARGE SCALE SYSTEMS; OPTIMIZATION;

ARCHITECTURE SYNTHESIS; COMPLEXITY REDUCTION; INTERCONNECT DELAY; LOW-COMPLEXITY FILTER;

DIGITAL FILTERS;

EID: 17644372788     PISSN: 10636404     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

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