4-Gb/s track and hold circuit using parasitic capacitance canceller

ESSCIRC 2004 - Proceedings of the 30th European Solid-State Circuits Conference

Volumn , Issue , 2004, Pages 347-350

  Sato, Takahide ^a   Takagi, Shigetaka ^a   Fujii, Nobuo ^a   Hashimoto, Yasuyuki ^b   Sakata, Kohji ^b   Okada, Hiroyuki ^b  

^a TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

^b STARC   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERSION; BANDWIDTH; BROADBAND NETWORKS; BUFFER CIRCUITS; CAPACITANCE; ELECTRIC DISTORTION; ELECTRIC IMPEDANCE; ENERGY DISSIPATION; ENERGY UTILIZATION; SIGNAL TO NOISE RATIO;

NEGATIVE IMPEDENCE CONVERTERS (NIC); SIGNAL TO NOISE AND DISTORTION RATIO (SINAD); TRACK AND HOLD (T/H) CIRCUITS; ULTRA WIDE BAND (UWB) WIRELESS SYSTEMS;

CMOS INTEGRATED CIRCUITS;

EID: 17644364795     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)

1. L.Y.Nathawad, et al. "A 20 GHz Bandwidth, 4b Photoconductive- Sampling Time interleaved CMOS ADC," International Solid State Circuit Conference, Digest of Technical papers, pp. 320-321, 2003
2. H. Hagiwara, et al. "A Monolithic Video Frequency Filter Using NIC-Based Gyrators," IEEE Journal of Solid-state Circuits, vol. 23, no. 1, February 1988