메뉴 건너뛰기





Volumn 3, Issue , 2004, Pages 1689-1694

A virtual prototyping process for power supplies using an electronic Design Verification Testing (eDVT) system

Author keywords

Electronic Design Verification Test (eDVT); Intellectual Property (IP) Blocks; SIMPLIS; Virtual Prototyping

Indexed keywords

ELECTRONIC DESIGN VERIFICATION TEST (EDVT); INTELLECTUAL PROPERTY (IP) BLOCKS; SIMPLIS; VIRTUAL PROTOTYPING;

EID: 17444381562     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (8)

References (0)
  • Reference 정보가 존재하지 않습니다.

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.