An integrated power switching stage with multi-chip planar interconnection construction

Conference Proceedings - IPEMC 2004: 4th International Power Electronics and Motion Control Conference

Volumn 1, Issue , 2004, Pages 364-369

  Liang, Zhenxian ^a   Van Wyk, J D ^a   Lee, Fred C ^a   Boroyevich, D ^a  

^a VIRGINIA POLYTECHNIC INSTITUTE AND STATE UNIVERSITY   (United States)

Author keywords

Multi chip 3 D Interconnection; Planar Process Technology; Power switching module

Indexed keywords

COMPUTER SIMULATION; DIELECTRIC MATERIALS; ELECTRIC POWER FACTOR CORRECTION; ELECTRIC POWER SYSTEM INTERCONNECTION; ELECTRONICS PACKAGING; FIELD EFFECT TRANSISTORS; HEAT RESISTANCE; INDUCTANCE; METALLIZING; MICROPROCESSOR CHIPS; MOS DEVICES; POWER ELECTRONICS; THIN FILM DEVICES;

MULTI-CHIP 3-D INTERCONNECTION; PARASITIC INDUCTANCE; PLANAR PROCESS TECHNOLOGY; POWER SWITCHING MODULES;

SWITCHING;

EID: 17444376353     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

1. H. Taraseisky, "Power Hybrid Circuit Design and Manufacture," New York: Marcel Dekker, 1996.
2. A.B. Lostetter, F. Barlow and A. Elshabini, "An Overview to Integrated Power Module Design for High Power Electronics Packaging," Microelectronics Reliability, 40(2000) 365-379.
3. M.C. Shaw and B. C. Beihoff, "Packaging of Integrated Solid-State Power Assembly Cells: A Thermo-Mechanics Based Approach," Proc. IEEE, Vol. 89, No. 6, June 2001, pp. 856-863.
4. T. Stockmeier, "Present and Future of Power Electronics Modules," Proceedings, CPES Seminar, Sept. 17-19, 2000, Blacksburg, VA, USA, pp. 3-9.
5. th VPEC Seminar, Blacksburg, VA, Sept. 1999.
6. W. Daum, W. Burdick and R. Fillion, "Overlay High-Density Interconnect: A Chips-First Multichip Module Technology," IEEE Comput, Vol. 26, April 1993, pp. 23-29.
7. A. Ostmann and A. Neumann, "Chip in Polymer - the Next Step in Miniaturization," Advancing Microelectronics, Vol.29, No. 3, 2002, p.13.
8. H. Braunisch, S. Towle, R. Emery, C. Hu and G. Vandentop, "Electrical Performance of Bumpless Build-Up Layer Packaging," in Proc. IEEE Electronic Components and Technology Conference, San Diego, May 28-31, 2002, pp. 353-358.
9. Li-Rong Zheng and Hannu Tenhunen, "Single Level Integrated Packaging Modules for High Performance Electronic Systems," IEEE Transactions on Advanced Packaging, Vol.24, No.4, Nov. 2001, p.477.
10. Zhenxian Liang, Fred C. Lee and Guo-quan Lu, "Embedded Power-An Integration Packaging Technology for IPEMs," International Journal of Microcircuit & Electronic Packaging, Vol.23, No.4, 2000, pp.481-487.
11. B. Jayant Baliga, "Trends in Power Semiconductor Devices," IEEE Transaction on Electron Devices, Vol. 43 (10), 1996, pp.1717-1731.
12. P. Xu, W. Y. Chen, J. W. Shao, P. L. Wong, B. Yang and F. C. Lee, "Development of 1kW Front-end Module for DPS Testbed," Proceedings of 2000 CPES Power Electronics Seminar, Blacksburg, VA, USA, p.116.
13. Y. Pang, J. Chen, E. Scott, K. Thole, and D. Boroyevich, "Electrical and Thermal Layout Design and Optimization Considerations for DPS Active IPEM," Procs. Of IMECE 2002 ASME International Mechanical Engineering Congress & Exposition, New Orleans, LA, USA, Nov. 17-22, 2002.