Sub-50 ps single poly planar bipolar technology

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 1988, Pages 740-743

  Chen, T C ^a   Tang, D D ^a   Chuang, C T ^a   Cressler, J D ^a   Warnock, J ^a   Li, G P ^a   Biolsi, P E ^a   Danner, D A ^a   Polcari, M R ^a   Ning, T H ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS, DIGITAL; LOGIC CIRCUITS, EMITTER COUPLED; LOGIC DEVICES--GATES;

LDD STRUCTURE; N-P-N TRANSISTOR; P-N-P TRANSISTOR; SILICON FILLED TRENCH STRUCTURE; SINGLE POLY PLANAR BIPOLAR TECHNOLOGY;

TRANSISTORS, BIPOLAR;

EID: 17144436000     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)